FPGA & CPLD
Products (6352)
EP910LI44 - Classic EPLD, 24 Macrocells, PLCC-44 | Altera / Intel
The Altera EP910LI44 is a member of the Classic EPLD family of CMOS Erasable Programmable Logic Devices, featuring 24 macrocells in a 44-terminal PLCC (J-lead) package. It supports up to 12 dedicated inputs and 24 bidirectional I/O pins, for a combined maximum of 36 inputs and 24 outputs. The device is fabricated on advanced CMOS technology and is part of the original Altera Classic EPLD series, now owned and supported by Intel following the 2015 acquisition of Altera. A programmable logic device (PLD) is a general-purpose digital IC whose logic function and interconnects are defined by the user after manufacture. The Altera Classic family belongs to the broader category of programmable logic devices (PLDs), which sit hierarchically between discrete logic gates (74-series TTL) and higher-density FPGAs. Within that taxonomy, the EP910 is a CMOS One-Time-Programmable (OT PLD) PAL-type architecture positioned for glue-logic integration in 5V systems where deterministic pin-to-pin propagation delay and low cost outweigh the need for SRAM-based re-programmability. Key features of the EP910LI44 include 24 macrocells, a maximum propagation delay in the range of 35 to 50 ns depending on speed grade (the suffix -30 / -35 / -40 indicates tpd), up to 24 flip-flops for registered logic, and support for 2 global clock pins. The device operates from a single 4.75 V to 5.25 V supply (industrial version 4.5 V to 5.5 V) and is available in commercial (0 °C to +70 °C) and industrial (-40 °C to +85 °C) temperature grades, as denoted by the L in the part number. Architecturally, the EP910 implements a sum-of-products AND/OR array feeding 24 output macrocells, each of which can be configured as combinational, registered, or I/O. The PAL-type structure gives every macrocell a fixed, predictable fan-in, allowing designers to compute worst-case propagation delay before synthesis - an important advantage over early FPGAs. Programmable interconnect distributes signals across the device with uniform delay, simplifying timing closure for state machines, address decoders, and bus-interface glue logic. Typical applications include 24 mA bus-interface drivers, state-machine controllers, address decoding in 5 V microprocessor systems, and replacement of multiple 74-series TTL packages. Because the EP910 is erasable (UV window on ceramic variants) or one-time programmable (plastic OTP), it suits both prototyping and low-to-medium volume production. Industrial users find the LI temperature grade suitable for factory-floor equipment, telecom peripherals, and consumer-electronics mainboards. When designing with the EP910LI44, plan power-rail decoupling with a 0.1 µF ceramic capacitor close to each supply pin and a bulk 10 µF electrolytic near the package. The EP910 has no internal pull-ups on I/O pins, so external 10 kΩ pull-ups are recommended on unused inputs to prevent floating CMOS inputs. Designers must also respect the 5 V VCC range; connecting to 3.3 V logic requires a level-translator, which the EP910 does not include. This page synthesizes distributor pricing, JTAG/ISP programming alternatives, and practical design notes for the EP910 Classic EPLD family that are not consolidated in the original manufacturer datasheet.
EP910LI44-35 - 24-Macrocell Classic EPLD, 35ns, PLCC-44 | Intel / Altera
The Intel / Altera EP910LI44-35 is a 24-macrocell Classic-series Erasable Programmable Logic Device (EPLD) fabricated on advanced CMOS technology and housed in a 44-pin PLCC package. It delivers a maximum clock frequency of 37 MHz with a propagation delay of 35 ns (tPD), supporting up to 2 external clocks and offering a PAL-type macrocell architecture for high-speed, low-power logic integration. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines the integration density of a PLD with the erasability of UV-erasable EPROM technology. Classic EPLDs sit within the broader programmable logic hierarchy: PAL < EPLD < CPLD < FPGA. They are typically deployed as glue logic, state-machine controllers, and bus-interface bridges where deterministic timing, low standby power, and instant-on (zero-configuration) behavior are required - qualities that modern SRAM-based FPGAs cannot match without an external boot PROM. Key features of the EP910LI44-35 include 24 macrocells organized in a PAL-type logic array, 10 dedicated input pins, 24 I/O pins, a tPD of 35 ns, a maximum internal counter frequency of 37 MHz, and CMOS-level I/O. The device supports in-system programmability via the Altera programming algorithm and is offered in both commercial and industrial temperature grades. The PLCC-44 (J-lead) package provides reliable through-hole soldering for legacy and industrial designs. Architecturally, the EP910 uses Altera's Classic macrocell with a product-term array feeding an OR gate, a programmable register, and a tri-state output buffer. Each macrocell supports D, T, JK, or SR flip-flop modes. The I/O architecture supports true bidirectional and registered I/O, and the device includes global clock networks routed through dedicated pins for low-skew distribution. Power consumption is typically below 200 mW at full operation, with CMOS standby currents in the microamp range when the device is not switching. Typical applications for the EP910LI44-35 include legacy industrial control, military/aerospace systems with long lifecycle requirements, telecom infrastructure glue logic, address decoding and bus arbitration in 8086/68k-based designs, and replacement of discrete 74LS/74HC logic in cost-sensitive applications. The 35 ns speed grade is well-matched to microcontrollers and microprocessors of the 1980s-1990s generation. When designing with this EPLD, ensure that the design fits within 24 macrocells and uses only the supported product-term count per macrocell. Use the MAX+PLUS II or Quartus legacy support tools to compile the design, and program the device using an Altera-compatible programmer. The PLCC-44 socket is recommended for prototyping. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes not found in the manufacturer datasheet, helping engineers sustain long-lifecycle EPLD-based systems.
EP910PC-0 - Classic EPLD, 24 Macrocells, 40-Pin PDIP | Altera
The Altera EP910PC-0 is a Classic-series Erasable Programmable Logic Device (EPLD) that delivers 24 macrocells and approximately 900 usable gates in a 40-pin Plastic DIP (PDIP-40) package. It is fabricated on advanced CMOS technology, offers 100% TTL emulation, and integrates multiple PAL/GAL-type devices into a single low-power, high-speed solution. The "PC" suffix denotes the PDIP-40 plastic commercial package, while "-0" indicates the slowest speed grade in the Classic EPLD family. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that combines multiple PAL/GAL-style AND/OR arrays with a shared programmable interconnect and a fixed OR array of macrocells. EPLDs sit in the taxonomy below modern CPLDs and FPGAs: programmable logic -> CPLD/EPLD -> PAL/GAL replacement -> logic integration IC. The Classic EPLD family was Altera's flagship low-density glue-logic replacement family in the late 1980s and 1990s, offering 100% TTL-compatible I/O and in-system erasability via a quartz window or, for plastic packages, one-time-programmable (OTP) UV-erasable silicon. Key features of the EP910PC-0 include 24 macrocells, 10 dedicated input pins, 24 I/O pins, a maximum propagation delay in the slowest ("-0") speed grade, 5V single-supply operation, and TTL-compatible logic thresholds. The device is implemented in CMOS technology for low power consumption, with each macrocell containing a programmable AND/OR array and a flip-flop. The Classic EPLD macrocell architecture enables pin-to-pin replacement of multiple 20- and 24-pin PAL/GAL devices, dramatically reducing board area and part count in legacy logic designs. Typical applications include TTL glue-logic replacement, bus-interface decoding, state-machine implementation, address decoding for microprocessor systems, and consolidation of multiple PAL/GAL devices in industrial control, telecommunications, and military/aerospace systems. The PDIP-40 through-hole package is favored for prototype development, breadboarding, and legacy systems where socketed parts simplify field serviceability. When designing with the EP910PC-0, engineers should note that the "-0" speed grade is the slowest available; for time-critical paths, the "-15", "-20", "-25", "-30", or "-35" grades provide progressively faster propagation delays in the same PDIP-40 footprint. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes for engineers maintaining or replicating legacy Altera Classic EPLD designs.
EP910PC-15 - 900-Gate Classic EPLD, 15ns PDIP | Altera
The Altera (now Intel) EP910PC-15 is a 900-usable-gate member of the Altera Classic EPLD family, a high-performance CMOS erasable programmable logic device offering pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz. The "-15" speed grade denotes the 15 ns tpd tier, and the "PC" suffix indicates a plastic dual in-line package (PDIP). The Altera Classic family targets high-speed, low-power logic integration, allowing designers to consolidate multiple PAL- and GAL-type devices into a single non-volatile part with densities spanning 300 to 900 usable gates. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural simplicity of a PLA (programmable AND / fixed OR) with on-chip macrocells and a one-time- or UV-erasable CMOS process. In the system hierarchy, EPLDs sit between simple SPLDs/PALs and modern FPGAs, historically serving as glue-logic replacements that retain their configuration without a boot PROM. The Classic family is fabricated on advanced CMOS technology and supports 100% TTL emulation, making the EP910 a direct substitute for clusters of 20-pin and 24-pin PAL/GAL devices. Key features of the EP910PC-15 include 24 macrocells, 10 dedicated input pins, 12 dedicated I/O pins, and a maximum toggle frequency of 100 MHz. The device operates from a single 5 V supply (VCC range 4.75 V to 5.25 V), draws Icc of typically 80 mA, and is packaged in a 24-pin, 0.300-inch-wide PDIP with through-hole leads. Programming is performed via the Altera Logic Programmer card on a standard PC parallel port. Architecturally, the EP910 implements a sum-of-products PLA with a global interconnect and per-macrocell flip-flops with configurable D/T/JK/SR modes. Programmable output slew-rate control reduces ground bounce on heavily-loaded buses, and unused pins can be left open without damage - though the datasheet recommends enabling the internal pull-up resistor via the configuration bit. Typical applications include TTL-logic replacement, address decoding for microprocessor systems, state-machine controllers, and bus-interface glue logic. Industrial control boards from the 1990s frequently use the EP910 as a peripheral decoder or interrupt controller. Because the part is in sustained production for legacy and long-lifecycle programs, it remains a popular choice for military, aerospace, and industrial sustainment designs. When designing with the EP910PC-15, observe the 0.3-inch PDIP-24 footprint and provide a 0.1 uF decoupling capacitor adjacent to VCC. The device is obsolete on Altera's modern price book; long-term procurement should target franchised distributors holding date-code inventory rather than the open market.
EP910PC-15T - 24-Macrocell EPLD, 15ns, PDIP-40 | Altera Classic
The Altera EP910PC-15T is a member of the Altera Classic EPLD family, an erasable programmable logic device (EPLD) with 24 macrocells and 10 dedicated input pins, fabricated on advanced CMOS technology and housed in a 40-pin plastic DIP (PDIP-40) package. Key headline specifications include a 15 ns pin-to-pin logic delay (tPD), a 24-macrocell AND-array architecture, and 10 dedicated input pins that fan into a programmable AND array feeding the 24 macrocell output registers. The '-15T' suffix denotes the 15 ns speed grade with Tape and Reel packaging. An EPLD (Erasable Programmable Logic Device) is a member of the programmable logic hierarchy, sitting between simple PLDs (PAL/GAL) and modern FPGAs/CPLDs. EPLDs use a sum-of-products architecture with a programmable AND array feeding fixed OR gates and output macrocells, packaged in UV-erasable or one-time-programmable CMOS silicon. The Classic family was Altera's second-generation EPLD line, replacing discrete TTL/CMOS gate arrays with single-chip, user-programmable logic for glue functions, state machines, and bus-interface logic. Key features include 24 macrocells each containing a programmable flip-flop with separate feedback, output enable, and programmable output polarity, plus 10 dedicated input pins (no input/output pin multiplexing) that simplify pin-locked designs. Device programming uses the Altera LogicMap or MAX+PLUS II design flow with industry-standard JEDEC fuse-map files. The EP910 also supports security-bit protection to lock the design after programming. Architecturally, the EP910 implements a global bus-driven AND plane with 72 product terms feeding 24 macrocells, yielding 24 registered outputs that can be configured as combinational (bypass register) or registered. The device is non-volatile (UV-erasable on ceramic-windowed versions, OTP on plastic packages), operates from a single 5 V supply, and delivers TTL-compatible I/O with 24 mA sink current per output. Typical applications include bus-interface glue logic, address decoding for microprocessor systems, peripheral control state machines, and replacement of multiple discrete 74LS/74F TTL parts. Modern designs typically substitute the EP910 with a CoolRunner-II CPLD or MAX II CPLD, but the Classic EP910 remains in service for legacy industrial, military, and avionics systems where pin-compatible replacements are required. Design considerations: the 15 ns speed grade is the slowest in the EP910 family (the family spans 10-25 ns); the suffix '-15T' includes tape-and-reel packaging. Plan for end-of-life risk - Altera discontinued the Classic EPLD family years ago, so sourcing is limited to authorized distributors and the broker/excess market. This page synthesizes datasheet parameters, drop-in Altera Classic family variants, parametric comparison data, and practical design notes not found in a single manufacturer document.
EP910PC-20 - Classic EPLD, 900 Gates, 20ns DIP-24 | Altera
The Altera EP910PC-20 is a 900-usable-gate Classic EPLD from the Altera Classic device family, supplied in a 24-pin PDIP (PC) package with a 20 ns pin-to-pin propagation delay. The Classic family delivers high-speed, low-power CMOS logic integration for glue-logic and bus-interface applications where multiple PAL or GAL devices would otherwise be required. A Classic EPLD (Erasable Programmable Logic Device) is a one-time-programmable (windowed EPROM-based) or UV-erasable CMOS PLD that replaces discrete SSI/MSI logic and small PAL/GAL arrays. EPLDs sit in the programmable logic hierarchy below CPLDs and FPGAs, offering non-volatile, deterministic logic with predictable timing. The Classic family specifically targets pin-to-pin speeds competitive with TTL and 74-series logic while consuming CMOS standby power. Key features of the EP910PC-20 include 24 pins, 16 dedicated inputs and 8 dedicated outputs (configurable as I/O depending on family mode), 900 usable gates, 100% TTL compatibility, and a 20 ns worst-case tPD (suffix "-20" speed grade). The part is fabricated on advanced CMOS technology and provides pin-to-pin logic delays suitable for state-machine decoding, address decoding, and bus-interface glue logic. The EP910 family integrates 300 to 900 usable gates, replacing multiple PAL/GAL devices with a single package. The EP910 architecture combines a sum-of-products AND/OR array with output macrocells featuring programmable polarity, registered or combinatorial outputs, and feedback paths. Programming is performed via a standard EPROM programmer using the JEDEC fuse-map format, and the device is non-volatile at power-up. The Classic family includes 100% TTL I/O compatibility and supports both 5V-only and mixed-voltage system designs. Typical applications include address decoding for microprocessor systems, bus arbitration, state-machine controllers, peripheral interface glue logic, and replacement of multiple PAL/GAL devices with a single EPLD. The PDIP-24 footprint supports through-hole PCB assembly, breadboard prototyping, and legacy system maintenance where socketed logic must remain in place. Designers should select the -20 speed grade when a 20 ns maximum tPD is sufficient for the target system clock or address-to-enable timing. Slower grades (-25, -30, -35) offer lower cost where timing margins permit. Faster -15 and -12 grades exist for tighter timing budgets. This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not found in the manufacturer datasheet alone.
EP910PC-20T Classic EPLD | Altera | Logic Integration
Altera EP910PC-20T is a member of the Classic EPLD family, a CMOS programmable logic device intended for high-speed, low-power logic integration. The verified search data identifies the family as supporting high-speed, low-power integration and as using advanced CMOS technology. It is described as a solution for integrating multiple PAL- and GAL-type devices, with Classic EPLD densities ranging from 300 to 900 usable gates. The EP910PC-20T ordering information specifically denotes the PC package and 20 ns speed grade, but the exact package pin count, electrical limits, memory architecture, and I/O count are not present in the supplied web excerpts. [DATA_NEEDED: package pin count and package dimensions]. An EPLD is an erasable programmable logic device: an integrated circuit whose logic functions are configured by the user and can be erased and reprogrammed. EPLDs sit within the programmable logic hierarchy between simple PLDs and larger FPGA devices. They combine programmable AND/OR logic, fixed interconnect, and input/output blocks in a nonvolatile architecture, making them useful for replacing multiple discrete PAL and GAL devices. The Classic EPLD family provides a compact way to implement glue logic, registered state machines, decoders, counters, and interface conditioning in a single programmable component. The EP910PC-20T is presented as a high-speed, low-power Classic EPLD. Its family-level positioning targets logic integration rather than the large sequential or signal-processing workloads commonly addressed by FPGAs. The supplied material states that the family supports 100% TTL emulation and that the EP910PC provides pin-to-pin logic integration for multiple PAL- and GAL-type devices. The 20 ns ordering suffix is treated as the device's specified speed grade, but a precise maximum operating frequency, propagation delay measurement condition, and power-consumption value are not available in the verified excerpts. The CMOS fabrication process supports the family's low-power objective while providing the speed needed for conventional TTL-compatible digital logic. Unlike a fixed-function logic IC, the EP910PC-20T can be programmed for a particular board's decoding, control, or interface requirements. Unlike an FPGA, its smaller Classic EPLD architecture is generally associated with simpler logic integration and a more focused capacity range, although the supplied data does not state a direct comparison of internal resources. Potential applications include legacy TTL logic consolidation, programmable address decoding, state-machine control, industrial control interfaces, and replacement of several PAL- or GAL-type devices on a board. The part is especially relevant to maintenance and redesign work involving existing Altera Classic EPLD designs, where changing the footprint or programming architecture may require board or firmware changes. Before new production use, verify the exact package drawing, supported programmer, software toolchain, and lifecycle status. For design-in, confirm that the selected package, pinout, operating voltage, temperature range, timing grade, and programming procedure match the existing implementation. Do not infer electrical limits from the family description. Use the manufacturer datasheet and an approved programming workflow before relying on the part for a new design. This page combines the verified EP910PC-20T search evidence, family-level application context, explicit missing-data markers, and replacement-screening guidance. It is intended to help engineers distinguish confirmed facts from parameters that require a full datasheet or device-specific cross-reference check.
EP910PC-25 - 900-Gate Classic EPLD, 25ns, PDIP-24 | Intel / Altera
The Intel / Altera EP910PC-25 is a 900-usable-gate member of the Classic EPLD (Erasable Programmable Logic Device) family, supplied in a 24-pin plastic DIP (PDIP-24) package with a 25 ns pin-to-pin logic delay. It is fabricated on advanced CMOS EPROM technology and is intended for high-speed, low-power logic integration, replacing multiple PAL/GAL devices with 100% TTL emulation. What is an EPLD? An EPLD is an Erasable Programmable Logic Device - a non-volatile programmable logic IC that sits in the hierarchy between simple PLDs (PAL/GAL) and modern FPGAs. It uses EPROM/EEPROM cells to store the AND/OR array fuse pattern, can be erased with UV light, and offers deterministic pin-to-pin timing ideal for glue-logic, bus decoding, and state-machine applications. The Classic family occupies the legacy PAL-replacement niche and is widely used in industrial control, instrumentation, and legacy system designs. Key features include 24 macrocells, 10 dedicated inputs, 12 dedicated input/output pins (bidirectional), 900 usable gates, 4800 integration gates (typical), and 100% TTL-compatible I/O. The EP910PC-25 provides 25 ns tPD (pin-to-pin delay) and operates at fMAX around 33.3 MHz with a 5 V +/- 10% supply. The CMOS EPROM process ensures low standby power, and the ceramic/erasable variants are suitable for prototype development while the plastic PDIP-25 suffix targets production. Architecturally the EP910 uses a sum-of-products (AND-OR) array feeding a fixed set of macrocells with programmable output polarity, feedback, and output enable. Output logic macrocells (OLMCs) can be configured as registered or combinatorial, allowing sequential and combinatorial logic in the same device. The deterministic timing model allows classic synthesis tools and Abel/CUPL/PLDshell design flows. Typical applications include TTL glue-logic replacement, address decoding for microprocessor/microcontroller buses, peripheral interface adapters (PIA), state machines in industrial controllers, and legacy 5V system integration. The PDIP-24 form factor supports through-hole assembly for repair-friendly and industrial designs. Design consideration: The "PC" suffix indicates PDIP-24 plastic commercial-grade, while the "-25" indicates 25 ns tPD. The part is windowless (one-time-programmable from the user's perspective) since the plastic package blocks UV erasure - plan accordingly for prototyping with a ceramic-windowed variant (DIP/LI). This page consolidates distributor pricing for the EP910PC-25, cross-brand EPLD drop-in alternatives sharing the PDIP-24 footprint, and practical design notes covering programming, supply decoupling, and pinout that complement the manufacturer datasheet.
EP910PC-30 - 24-Macrocell Classic EPLD, 30ns, PDIP-40 | Altera
The Altera EP910PC-30 is a Classic-family Erasable Programmable Logic Device (EPLD) delivering 24 macrocells and approximately 450 usable gates in a 40-pin Plastic DIP (PDIP-40) package. The "PC" suffix denotes the plastic through-hole package, while "-30" designates a 30 ns worst-case pin-to-pin propagation delay, corresponding to a maximum counter frequency of 33.3 MHz. The device operates from a single 5 V supply and supports 100% TTL emulation for direct drop-in replacement of discrete PAL and GAL logic arrays. What is an EPLD? An EPLD (Erasable Programmable Logic Device) is a member of the programmable logic family that sits architecturally between simple PAL/GAL SPLDs and higher-density CPLDs. An EPLD combines multiple macrocell-based logic blocks into a single package, allowing designers to consolidate dozens of 7400-series TTL functions into one UV-erasable IC. EPLDs occupy the middle rung of the hierarchy: SPLD (PAL/GAL) -> EPLD (Classic, MAX) -> CPLD (MAX II/3000, MAX V) -> FPGA. The EP910 is part of Altera's Classic family, the second generation of the MAX architecture. Key features include 24 macrocells organized into four Logic Array Blocks (LABs) with 36 dedicated input pins and 12 bidirectional I/O pins, programmable output macrocells with flip-flops (D, T, JK, SR), asynchronous clear and preset, programmable I/O architecture supporting combinatorial or registered outputs, and on-board logic test circuitry to verify AC parameters during production. The EP910 implements sum-of-products logic via a programmable AND/OR array with feedback paths that enable complex state machine implementation. Typical applications include glue-logic consolidation for 8086/68000-era microprocessor systems, address decoding and bus interfacing, state-machine controllers, peripheral replacement of multiple PAL/GAL devices, and legacy industrial control retrofits. Designers targeting modern designs typically migrate to MAX II or MAX V CPLDs, but the EP910 remains in service for repair of installed equipment and exact-form-factor replacements. When designing with the EP910, ensure logic equations fit within the available 24-macrocell / 36-input product-term budget; synthesis tools such as MAX+PLUS II perform fitting and report resource utilization. Programming requires a compatible EPROM/UV eraser or Altera programming hardware, since Classic EPLDs are erasable rather than in-system programmable. The 5 V supply tolerance (±10%) is critical for TTL compatibility, and decoupling capacitors should be placed within 0.5 inches of each VCC/GND pair. This page synthesizes distributor pricing, current lifecycle status from Rochester Electronics, drop-in same-package alternatives within the EP910 family, and practical design notes not consolidated in the original Altera datasheet.
EP910PC-30T - 900-Gate Classic EPLD, 30ns, DIP-40 | Intel (Altera)
The Intel (formerly Altera) EP910PC-30T is a 900-usable-gate Classic EPLD with 30 ns pin-to-pin propagation delay, 24 macrocells, 24 I/O pins, and 12 dedicated inputs, fabricated on an advanced CMOS process and packaged in a 40-pin plastic DIP (PDIP-40). It is designed for high-speed, low-power logic integration in through-hole legacy designs and supports a maximum clock frequency of 33.3 MHz, 100% TTL emulation, and pin-to-pin compatibility with other EP910 speed grades. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic that replaces multiple discrete PAL/GAL devices with a single CMOS IC; in the broader taxonomy it sits between simple PLDs (PAL/GAL) and modern CPLDs/FPGAs as an early high-density, UV-erasable logic family. The Classic family provides densities from 300 to 900 usable gates and propagation delays as low as 10 ns, making it a workhorse for industrial control, glue logic, and bus-interface bridging where modern FPGAs would be over-spec and over-priced. Key features include 240 product terms across 24 macrocells interconnected by a global programmable interconnect array, 100% TTL-compatible I/O, on-board logic test circuitry for AC verification during production flow, and programming compatibility with the MAX+PLUS II development system. The 'PC' package suffix denotes plastic DIP, while '-30T' indicates the 30 ns speed grade in tube packaging, identical to the commercial EP910PC-30 except for delivery format. Architecturally the EP910PC-30T uses a PAL-type AND/OR structure with a global bus connecting each macrocell, supported by a 5 V CMOS process that delivers low quiescent power compared to bipolar TTL PLDs. Each macrocell contains an XOR gate, a programmable flip-flop, an output enable, and a feedback path, allowing registered, combinational, and bidirectional I/O configurations within the same device. The Classic family's logic test circuitry allows verification of function and AC specifications during standard production flow. Typical applications include industrial control glue logic, address decoding and bus interfacing for legacy microprocessors (e.g., 8086, 68000, Z80 systems), state-machine replacement of discrete SSI/MSI logic, custom peripheral controllers in test equipment, and pin-compatible upgrades of older EP310/EP320 designs. It is commonly used to consolidate multiple 16L8/20L8 PALs into a single device, simplifying PCB layout and reducing part count. When designing with this device, ensure your design tools support the Classic device family (MAX+PLUS II or compatible legacy software). Verify the 30 ns propagation delay meets your timing budget against the slowest clock edge in your system. Plan for end-of-life sourcing: the Classic family is mature and inventory is mostly distributor or aftermarket stock; second-source or upgrade paths should be evaluated for new long-life designs. This page synthesizes distributor pricing, same-package drop-in alternatives within the EP910 family, and practical design notes not found in the original Altera datasheet, giving engineers a single reference for sourcing and implementing the EP910PC-30T.
EP910PC-35 - 35ns 24-Macrocell EPLD | Altera | Classic EPLD
The Altera EP910PC-35 is a 24-macrocell high-performance CMOS Erasable Programmable Logic Device (EPLD) from the Classic EPLD family, specified at 35 ns pin-to-pin propagation delay. Housed in a 40-pin Plastic DIP (PDIP) package, the EP910PC-35 delivers up to 37 MHz counter frequency and 100 MHz internal performance, making it a staple glue-logic building block for legacy industrial, telecom, and test equipment designs. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device from the pre-FPGA era, providing PAL-type sum-of-products logic with on-chip macrocells, a programmable AND/OR array, and reconfigurable I/O architecture. EPLDs sit in the programmable logic hierarchy between simple PAL/GAL devices and modern FPGAs, and the EP910 family specifically targets designs that need higher density and I/O count than 22V10-class devices while avoiding the complexity of SRAM-based FPGAs. The EP910PC-35 is the UV-erasable/OTP plastic-DIP variant of the EP910 family. Key features include 24 macrocells with 24 I/O pins, 12 dedicated inputs giving 36 total inputs, 240 product terms distributed across the AND-array, and 35 ns typical pin-to-pin logic delay. The PAL-type architecture with buried macrocell registers, combined with CMOS technology, provides low power consumption and high noise immunity. The device operates from a single 5V supply and is in-system programmable via Altera's classic A+PLUS or MAX+PLUS development tools. Architecturally, the EP910 family combines a global interconnect scheme with per-macrocell product-term allocation, allowing wide combinational and registered logic functions without the routing congestion of older PALs. Macrocell flip-flops can be configured as D, T, JK, or SR, with selectable clock polarity and asynchronous clear/preset — giving designers flexibility comparable to early 1990s PLDs. Typical applications include address decoding and bus interface logic in 5V embedded systems, replacement of multiple 22V10 / 16L8 PALs in industrial controllers, glue logic in legacy telecom backplanes, and prototyping or low-volume production where FPGAs are over-specified. The plastic DIP package simplifies hand-soldering and rework on through-hole boards. When designing with this device, ensure your programming tool supports the EP910 family — A+PLUS or MAX+PLUS legacy software is required. Note that plastic DIP packages are not windowed for UV erasure; use ceramic windowed CerDIP variants (EP910DC-35) during development and plastic for production. Decoupling: place a 0.1 uF capacitor on each VCC pin and minimize high-current switching near the device. This page synthesizes distributor pricing, drop-in same-family EPLD alternatives (EP910PC-30, EP910PC-25), cross-reference compatibility information, and practical design notes that complement the manufacturer datasheet for legacy designs.
EP910PC/PI - 900-Gate CMOS Classic EPLD | Intel | PDIP-40
The Intel (formerly Altera) EP910PC/PI is a 900-gate member of the Altera Classic EPLD family, fabricated on advanced CMOS technology and offering high-speed, low-power logic integration in a 40-pin PDIP through-hole package. It provides 24 macrocells, 48 flip-flops, 33.3 MHz fMAX, and 5 V operation with 100% TTL emulation and 10 mA/24 mA I/O drive strength. The 'PC' suffix denotes a 0 to 70 °C commercial-temperature PDIP package, while the dual 'PC/PI' marking covers both the commercial- and industrial-temperature options for the same footprint. A Classic EPLD (Erasable Programmable Logic Device) is a non-volatile, UV-erasable CMOS PLD that combines PAL/GAL-like AND/OR arrays with on-chip macrocell flip-flops, forming an early predecessor of today's flash-based CPLDs. Within the broader programmable-logic hierarchy, Classic EPLDs sit below MAX II/MAX V CPLDs and modern Cyclone/MAX FPGAs in density but above discrete 22V10 PALs in functional capability. They are typically programmed with the MAX+PLUS II development toolchain via a JTAG/ISP or device-programmer interface. Key features of the EP910PC/PI include 100% TTL-compatible I/O, JTAG-based boundary-scan testability, 24 dedicated input pins, 48 I/O pins, and 33.3 MHz system-clock performance. The CMOS EPROM-style configuration cell yields zero standby power on legacy unconfigured cells, and the on-board logic test circuitry allows AC specification verification during production flow. These attributes made the EP910 a popular glue-logic replacement for multiple PAL and GAL devices in 5 V industrial and telecom designs of the 1990s. Architecturally, the EP910 integrates a global programming array, a macrocell array with 24 flip-flops, an I/O control block, and dedicated input pins. The Classic architecture pioneered macrocell sharing, which became a defining feature of subsequent MAX-series CPLDs. Designers using the EP910PC/PI can implement 100% pin-to-pin logic integration while maintaining deterministic 25 ns propagation delays for state-machine and bus-interface logic. Typical applications include TTL/CMOS glue-logic replacement, address decoding, state machines, bus arbitration, and 5 V system controllers in industrial automation, telecommunications backplane controllers, and legacy military/aerospace systems (when the /883B-screened DM variants are used). The wide 5 V tolerance makes it well suited to 5 V-only legacy backplanes. When designing with the EP910PC/PI, ensure the device is programmed before PCB-level in-system programming is finalized, since legacy UV-windowed variants require a quartz-windowed CERDIP package for erasure. Decoupling should follow Altera's 0.1 µF per VCC pin guideline with a single 10 µF tantalum bulk capacitor. Pin-compatibility across the EP910 speed grades (-15, -20, -25, -30, -35) simplifies PC-grade PCB reuse.
EP910PC30T - 24 Macrocells CMOS Classic EPLD, 30ns DIP-24 | Altera
The Altera (Intel) EP910PC30T is a 30ns, 5V Classic EPLD with 24 macrocells and 24 I/O pins in a 24-pin PDIP through-hole package. It belongs to the Altera Classic device family, fabricated on advanced CMOS technology for high-speed, low-power logic integration in glue-logic and bus-interface roles. A Classic EPLD (Erasable Programmable Logic Device) is a one-time- or UV-erasable PLD that preceded modern CPLDs and FPGAs in the programmable logic hierarchy. The taxonomy runs: programmable logic device (PLD) -> EPLD -> Classic EPLD -> complex PLD (CPLD), positioning the EP910 as a mid-density, low-power, deterministic-delay glue-logic IC that bridges the gap between simple PAL/GAL devices and modern CPLDs such as the MAX 7000 series. Key specifications include 24 macrocells interconnected by a global programmable interconnect, 12 dedicated inputs, 24 I/O lines, up to 240 product terms, a maximum clock frequency of 33.3 MHz, and a propagation delay (tPD) of 30 ns. The device operates from a single 5V supply (typical VCC range 4.75 V to 5.25 V) and offers non-volatile, factory- or user-programmable AND/OR logic arrays. Architecturally, the EP910PC30T uses a PAL-type sum-of-products macrocell structure with a global bus connecting all 24 macrocells, enabling deterministic 30 ns pin-to-pin delays regardless of routing path. The CMOS EPROM-based cell array provides zero standby power once programmed and supports a JEDEC-standard programming algorithm compatible with standard device programmers. Typical applications include address decoding and bus-interface glue logic in 5V microprocessor systems, peripheral-chip replacement in legacy designs, state-machine and sequencer implementation, and industrial control logic where deterministic timing and 5V tolerance are required. The 30 ns speed grade makes it suitable for systems clocked up to 33 MHz. When designing with the EP910PC30T, note that the part is non-erasable (one-time-programmable, OTP) in most package options; only ceramic-windowed packages permit UV erasure. Designers should also confirm 5V I/O compatibility with modern 3.3V logic, as the EP910 lacks 5V-tolerant inputs that would interface directly with low-voltage rails. This page synthesizes distributor stock, same-package speed-grade alternatives, and practical design notes not found in the original 41-page Altera datasheet.
EP910PI-12T - 24 Macrocell Classic EPLD, 12ns tPD | Altera
The Altera EP910PI-12T is a 24-macrocell Classic-series Erasable Programmable Logic Device (EPLD) housed in a 40-pin plastic DIP (PDIP-40) package, with a 12 ns propagation delay and CMOS technology. It belongs to the Classic EPLD family that delivers high-speed, low-power logic integration for glue-logic and state-machine replacement applications. The 'PI' suffix indicates the PDIP-40 industrial-temperature package, and '-12T' indicates the 12 ns speed grade with a Tape-and-Reel or specific test/packaging suffix. An EPLD (Erasable Programmable Logic Device) is a one-time-or-UV-erasable PLD that preceded modern CPLDs and FPGAs. As a product category it sits between fixed logic gates and modern FPGAs in the programmable logic hierarchy: PLD -> EPLD -> CPLD -> FPGA. EPLDs typically offer macrocell-based combinational and registered logic with deterministic timing, non-volatile (UV-erasable) configuration, and instant-on behavior - making them suitable for legacy designs where simplicity and deterministic timing matter more than gate density. Key features of the EP910PI-12T include 24 macrocells interconnected via a global programmable interconnect array, 24 I/O pins, and 12 dedicated inputs supporting two clock domains. Fabricated in CMOS technology, it offers a typical 15 ns pin-to-pin propagation delay (commercial) with the -12 speed grade being the faster variant in this part family. The device supports both combinatorial and registered logic with feedback, and is in-system programmable via a standard JEDEC programming interface. Typical applications for the EP910PI-12T include address decoding, bus interfacing, state-machine control, and glue logic in legacy industrial, telecom, and embedded systems. Engineers selecting this part typically need exact timing behavior, deterministic logic, and pin compatibility with prior Altera Classic designs. It is fully compatible with industry-standard PLD development tools including the Altera MAX+PLUS II legacy flow. Designers should note that the EP910 series is part of the mature Altera Classic EPLD line, now NRND/EOL for new designs. For new designs, consider MAX II, MAX V, or MAX 10 CPLDs as modern equivalents. The PDIP-40 package simplifies prototyping on through-hole PCBs but limits automated assembly. Pricing reflects legacy/obsolete status and limited supply.
EP910PI-15T - 24-Macrocell Classic EPLD, 15ns | Altera
The Altera EP910PI-15T is a member of the Classic EPLD (Erasable Programmable Logic Device) family from Intel/Altera, providing 24 macrocells, 12 dedicated inputs, and 24 I/O pins interconnected by a programmable AND/OR logic array in a 40-pin plastic DIP package. It is fabricated on advanced CMOS technology and operates from a single 5V supply (4.5V to 5.5V), with a 15ns maximum pin-to-pin propagation delay (tPD) at industrial temperature ranges. A Classic EPLD is an electrically erasable programmable logic device that combines the architectural simplicity of sum-of-products (AND-OR) logic with non-volatile E2PROM memory cells, sitting historically between discrete PAL/GAL devices and modern SRAM-based FPGAs in the programmable logic hierarchy. The EP910 family sits in the classic programmable logic family and is the second largest density member of that series, used for glue-logic integration and state-machine consolidation on 5V systems that predate the 3.3V migration. Architecturally the part is one of the highest-density 5V-only erasable PLDs Altera shipped in the Classic line. Key features include 24 macrocells, a Programmable Interconnect Array (PIA) with deterministic tPD, 24 mA DC output drive per pin (TTL-compatible), pin-compatible JEDEC-standard programming, and 100% factory-tested logic. The device supports both combinatorial and registered logic with feedback, and includes dedicated input pins, output enable control per macrocell, and a global clear/preset. Programming is performed via standard JEDEC fuses using an Altera programming hardware or compatible third-party programmer. The EP910PI-15T is fabricated in a CMOS EEPROM process, draws relatively low standby current for a Classic EPLD, and is supplied in a through-hole 40-pin PDIP package (R-PDIP-T40) suitable for industrial and legacy designs. The PI suffix indicates the plastic DIP package, and the 15 speed grade denotes 15 ns tPD; the trailing T indicates tape and reel packaging for the through-hole part. Typical applications include industrial 5V control logic, glue-logic replacement for discrete 74LS/TTL gates, address decoding and bus interfacing, state-machine implementation, and legacy equipment repair/maintenance. Engineers choose this part when designing or maintaining 5V systems that need non-volatile, deterministic-timing logic without the complexity of an FPGA. When designing with the EP910PI-15T, account for the 15 ns propagation delay in worst-case timing paths and respect the 24 mA per-pin output current limit. Use the Altera MAX+PLUS II or classic development flow for design entry and JEDEC generation. For new designs consider a modern MAX II/V equivalent; for legacy board repair or pin-compatible 5V replacement the EP910PI-15T is a direct-fit option. This page synthesizes Altera datasheet parameters, distributor stock signals, same-package EP910 family variants as drop-in alternatives, and practical 5V glue-logic design notes not assembled in a single place on the manufacturer's datasheet alone.
EP910PI-20 - 24 Macrocell Classic EPLD, 20ns, PDIP-40 | Altera
The Intel / Altera EP910PI-20 is a 24-macrocell Classic EPLD (Erasable Programmable Logic Device) from the original Altera Classic device family, fabricated on advanced CMOS technology, housed in a 40-pin PDIP (Plastic DIP) through-hole package with a 20 ns pin-to-pin propagation delay grade. It targets high-speed, low-power logic integration in glue-logic and bus-interface applications where a small, deterministic PLD offers faster time-to-market than an FPGA. Background Knowledge: An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device, sitting in the broader taxonomy of programmable logic: PLD -> EPLD -> CPLD -> programmable logic -> semiconductor. EPLDs were the predecessors to today's CPLDs and offer a small number of macrocells with deterministic timing and zero power-on configuration delay, unlike SRAM-based FPGAs. They were widely used for address decoding, bus arbitration, state-machine control, and peripheral glue logic in 5V-era designs. The EP910 family is the 24-macrocell, 36-pin/40-pin member of the original Altera Classic series, with EP610 (16 macrocells) and EP1810 (48 macrocells) as siblings. Key features of the EP910PI-20 include 24 macrocells organized as 12 dedicated inputs and 24 bidirectional I/O pins (in the PDIP-40 footprint), 20 ns tPD (pin-to-pin delay), a 125 MHz internal counter frequency, and zero standby-power CMOS EPROM technology with UV-erasable windowed packages available for prototyping. The device is 5V-tolerant (VCC = 5V +/- 5%) and offers programmable macrocell flip-flops, product-term allocation, and configurable output polarity. The PI suffix indicates the industrial temperature grade (-40C to +85C). Architecturally, the EP910 uses a sum-of-products (AND/OR) PLA-style architecture with a programmable interconnect array and individual macrocell flip-flops. Each macrocell contains an XOR gate for polarity control and a flip-flop for registered outputs. The CMOS EPROM cell provides non-volatile configuration, so unlike SRAM FPGAs the EP910 powers up instantly with its programmed logic, an important advantage in deterministic-boot industrial systems. Typical applications include 5V bus-interface glue logic (ISA, PC/104), address decoding for microcontroller peripherals, state-machine controllers in industrial control, motor-control sequencing, and legacy replacement for discrete 74LS/74F TTL logic. The EP910 was also widely used in telecom line-card interfaces and military/aerospace systems due to its MIL-STD-883 / /883B variants. Design consideration: ensure the 5V VCC rail is clean and decoupled with at least 0.1 uF ceramic + 10 uF bulk capacitors close to the device. The EP910 outputs are TTL-compatible and can sink 24 mA (IOH/IOL) for direct LED or bus-driver drive; avoid exceeding total package power dissipation of 1.5W. Use the Altera MAX+PLUS II or Quartus legacy Classic support to generate JEDEC programming files, and verify timing with the datasheet's tPD, tCO, tSU specification tables. Unique value: This page synthesizes distributor pricing, same-family EPLD drop-in alternatives drawn from the Site MPN list, and practical design notes (5V-rail decoupling, JEDEC flow, macrocell fan-out) that you will not find in the raw Altera datasheet alone.
EP910PI-20T - 24 Macrocell Classic EPLD, 20ns, PDIP-40 | Intel
The Intel (formerly Altera) EP910PI-20T is a 24-macrocell Classic Erasable Programmable Logic Device (EPLD) from the Altera Classic EPLD family, fabricated on advanced CMOS technology and offered in a 40-pin PDIP (PI) plastic DIP package with a 20 ns propagation delay. The -20T suffix indicates the tpd speed grade (20 ns) and the Tape & Reel packaging variant per the original Altera ordering code; functionally identical to the EP910PI-20 (tube) part. A Classic EPLD (Erasable Programmable Logic Device) is a member of the early programmable logic family that sits hierarchically between discrete PAL/GAL devices and modern CPLD/FPGA. EPLDs combine multiple AND/OR macrocell arrays with a programmable interconnect and are used to replace dozens of SSI/MSI logic gates in glue-logic applications. The Classic family targets high-speed, low-power logic integration and offers CMOS-compatible I/O, deterministic timing, and one-time or UV-erasable programming. Key features of the EP910PI-20T include 24 usable macrocells, 48 product-term AND gates feeding shared OR arrays, 12 dedicated input pins, 20 I/O pins, a maximum toggle frequency around 62.5 MHz, 20 ns pin-to-pin propagation delay (tpd) and an industry-standard JEDEC map. It is fabricated in 1.5 micron CMOS EPROM technology, which yields low static power consumption and in-system programmable configuration via a standard EPROM programmer. The PDIP-40 (PI) package is a through-hole form factor that is convenient for prototype, breadboard and legacy industrial systems. Typical applications include bus decoding and address mapping on 8-bit and 16-bit microprocessor systems, glue logic replacement for legacy 74LS/74F TTL designs, custom state machines, I/O port expansion, and discrete gate integration in industrial controllers. The device's deterministic 20 ns delay makes it a predictable replacement for multiple 74LS-series packages. When designing with the EP910PI-20T, designers should validate timing against the Altera Classic EPLD datasheet macrocell switching characteristics and derate propagation delay by operating temperature. Note that the PI package has higher lead inductance than surface-mount equivalents, so high-speed outputs above 30 MHz should be evaluated for signal integrity. This page synthesizes distributor pricing, drop-in same-package alternatives (preferring variants on the XAIPART Site MPN list), and practical design notes not found in the original Altera datasheet.
EP910PI-25 - 24-Macrocell Classic EPLD, 25ns, PDIP-40 | Intel
The Intel (formerly Altera) EP910PI-25 is a 5 V CMOS Erasable Programmable Logic Device (EPLD) from the Altera Classic family, delivering 24 macrocells and 12 dedicated inputs with 24 bidirectional I/O pins, housed in a 40-pin Plastic DIP package. It features a 25 ns pin-to-pin propagation delay and operates at a maximum clock frequency of 40 MHz, providing high-speed, low-power logic integration for glue-logic and bus-interface designs. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic IC that sits between simple PLDs and full FPGAs in the programmable logic hierarchy: simple PLD (PAL/GAL) -> EPLD -> CPLD -> FPGA. EPLDs use a sum-of-products macrocell fabric with EPROM or EEPROM cells to retain configuration without external memory, making them ideal for deterministic logic replacement, decoder functions, and small state-machine integration in industrial and telecom systems. Key features of the EP910PI-25 include 24 macrocells interconnected by a global programmable interconnect array, 12 dedicated input pins feeding the AND array, 24 bidirectional I/O pins with individual output enable control, a JTAG-compatible in-system programmability path on speed grades, and a maximum toggle frequency of 40 MHz on internal registers. The device supports 5 V nominal VCC operation with TTL-compatible I/O and is fabricated on an advanced CMOS process for low quiescent current. The EP910 architecture uses a single global bus connecting all 24 macrocells to dedicated and I/O pins, with each macrocell featuring configurable flip-flop polarity, feedback paths, and output enable control. This structure yields predictable, deterministic timing with the tPD value acting as the worst-case delay across all paths, simplifying static timing closure in legacy designs compared with modern SRAM-based FPGAs. Typical applications include peripheral glue logic in 5 V VME/cPCI backplanes, address decoding and interrupt steering in Motorola 68000/Intel x86 systems, bus protocol translation between TTL peripherals, and replacement of discrete 74LS/74F logic clusters. The 5 V VCC and TTL I/O make it compatible with legacy logic families still used in industrial automation and telecom line cards. When designing with the EP910PI-25, ensure that all VCC and GND pins are decoupled with 0.1 uF ceramic capacitors placed within 5 mm of the package. The 25 ns tPD must be budgeted across two-level logic paths; use the Altera MAX+PLUS II development system for fit, place, and timing analysis. Note that this part is widely considered obsolete, so lifecycle status should be verified before new production. This page synthesizes authorized distributor inventory, drop-in alternatives, parametric comparisons and design notes for the EP910PI-25 that are not collated in the original Altera datasheet or third-party listings.
EP910PI-25T - 24-Macrocell Classic EPLD, 25ns, DIP-40 | Altera
The Altera EP910PI-25T is a 24-macrocell Classic EPLD (Erasable Programmable Logic Device) from the Altera Classic EPLD family, fabricated on advanced CMOS technology and housed in a 40-pin, 600-mil plastic dual-in-line (DIP) package with a 25 ns propagation delay speed grade and industrial temperature rating. It implements over 900 equivalent gates of SSI/MSI logic functions with up to 36 inputs and 24 outputs, providing high-speed, low-power logic integration for glue-logic, decoder, state-machine and bus-interface applications. A Classic EPLD (Erasable Programmable Logic Device) is a type of programmable logic that belongs to the broader hierarchy of programmable logic devices (PLDs), sitting above discrete SSI/MSI logic gates and below modern CPLDs and FPGAs in integration density. EP910-family EPLDs were designed for high-speed combinatorial and registered logic replacement where the application requires deterministic, fixed-pin timing that an FPGA cannot guarantee. The EP910 integrates a programmable AND/OR array, 24 flip-flop-equipped macrocells, and a flexible interconnect scheme, giving designers 38 dedicated input pins and 24 I/O pins. Per the manufacturer datasheet, the EP910 offers typical CMOS static power consumption below 100 mW and operates from a single 5V supply, making it suitable for both battery-backed and line-powered industrial systems. Architecturally, the EP910 uses Altera's Classic MAX-like AND/OR structure with UV-erasable EPROM cells for programming; the "PI" suffix denotes plastic DIP packaging, "-25" denotes the 25 ns pin-to-pin propagation delay (tpd), and the "T" suffix denotes tape-and-reel packaging for high-volume assembly. Typical applications include industrial control glue logic, address decoding for microprocessor systems, state-machine implementation, bus-interface and arbitration logic, and legacy replacement of discrete 74LS TTL logic. The 40-pin DIP form factor supports both through-hole PCB assembly and socketed prototyping on breadboards and development systems. Design consideration: the EP910 uses a single +5V VCC supply; designers must observe the 25 ns tpd budget when targeting bus-cycle or memory-interface timings. For new designs, designers should evaluate whether a modern CPLD such as Altera MAX V or Lattice ispMACH 4000 offers better cost-per-gate; however, the EP910 remains in service in long-lifecycle industrial, military and avionics systems. This page synthesizes current distributor stock, same-family drop-in alternatives, and practical design notes not consolidated in the manufacturer datasheet.
EP910PI-30T - 24-Macrocell Classic EPLD, 30ns, PDIP-40 | Altera
The Altera (Rochester Electronics) EP910PI-30T is a 24-macrocell Classic-series Erasable Programmable Logic Device (EPLD) with a 30ns propagation delay, fabricated on a low-power CMOS process and housed in a 40-pin PDIP (Plastic DIP) through-hole package. It integrates 24 macrocells, 480 usable gates and 10 dedicated input pins, providing high-speed, low-power logic integration for glue-logic and state-machine replacement. The 'PI' suffix denotes the industrial ceramic-windowed package option, while the '-30' suffix specifies the 30ns tPD speed grade. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that retains its configuration without external memory and is electrically erasable via UV exposure (windowed packages) or, in later erasable variants, electrically in-circuit. Within the broader component taxonomy, an EPLD sits below a CPLD (Complex PLD) and well below an FPGA in density, but offers faster deterministic pin-to-pin timing and instant-on behaviour, making EPLDs ideal for address decoding, bus interfacing, and control-logic replacement of discrete TTL/CMOS gates. Key features of the EP910PI-30T include 24 macrocells with configurable D/T/JK flip-flops, 30ns combinational propagation delay (tPD), 20ns register (clock-to-output) delay, and ten dedicated input pins feeding an AND-OR-NOT sum-of-products structure. The device operates from a single 5V supply (VCC = 4.75V to 5.25V), supports in-system 100% generic testability, and is fully compatible with the Altera MAX+PLUS II Classic device development flow. The Classic architecture gives predictable, deterministic timing because each macrocell has a fixed product-term allocation. Typical applications include TTL/CMOS gate and SSI/MSI replacement, address decoding for microprocessor buses, bus-interface glue logic, state-machine implementation, and industrial control systems. The ceramic-windowed PDIP package also supports field reprogramming after UV erasure during prototyping. When designing with this part, plan for one extra I/O pin per macrocell versus the dedicated-pin count, and add a 0.1uF decoupling capacitor close to VCC. The 30ns speed grade is the slowest Classic EP910 variant and is intended for cost-sensitive legacy designs; for higher speed, choose EP910PC-25, EP910PC-20 or the EP910LC/LI -15/-20 grades. This page synthesizes distributor pricing, verified drop-in alternatives from the Altera/Rochester Classic EPLD family, and practical design notes that supplement the original Altera datasheet.
EP910PI-35 - 24-Macrocell Classic EPLD, 35ns, PDIP-40 | Rochester/Altera
The EP910PI-35 is a Classic EPLD (Erasable Programmable Logic Device) manufactured by Altera (now Rochester Electronics) delivering 24 macrocells, 450 usable gates, and a 35 ns pin-to-pin propagation delay in a 40-pin PDIP (Plastic DIP) through-hole package. It is a CMOS, UV-erasable member of Altera's Classic EPLD family and operates from a single 5 V supply. The die is the original Altera EP910 architecture, offered by Rochester Electronics as a long-life-cycle, authorized continuation part for legacy designs. A Programmable Logic Device (PLD) is a digital integrated circuit whose logic function is defined by the customer after manufacture, allowing a single part to replace many discrete TTL/CMOS glue-logic ICs. EPLDs specifically use EPROM (UV-erasable) technology and sit in the programmable-logic hierarchy below modern CPLDs and FPGAs; the Classic EPLD family was Altera's first-generation product line and remains a building block in legacy industrial, telecom, and military designs where pin-compatible continuity is required. Key features include 24 macrocells organized as 12 dedicated inputs and 24 I/O pins (bidirectional), 450 usable gates, 35 ns tPD (propagation delay), 28.6 MHz fMAX, and 5 V CMOS I/O. The device is in-circuit programmable via a standard Altera programming hardware, and the ceramic windowed version allows erasure with UV light for re-use. The EP910 family predates JTAG and uses the legacy Altera programming interface. The PDIP-40 package gives the part a robust through-hole footprint suited to prototyping, MIL-spec assemblies, and long-lifecycle industrial control boards. Typical applications include address decoding and bus-interface glue logic in legacy 80C186/68k systems, control logic in industrial PLCs, state-machine replacement of TTL MSI, custom peripheral decoders in VME/cPCI backplanes, and avionics/military systems where the EP910 has been qualified for decades. Rochester Electronics' authorized stock ensures long-term availability for EOL-prone designs. When designing with this device, ensure the programming algorithm matches the EP910 family (legacy Altera software such as MAX+PLUS II is required), respect the 5 V supply tolerance, and provide adequate decoupling. Designers migrating to a modern equivalent should evaluate Altera/Intel MAX II or Lattice ispMACH 4000 CPLDs as the architectural successor; for true drop-in continuity, the EP910PC-35 (same die, plastic DIP) and EP910LI-35 (windowed ceramic DIP) remain in the family. This page synthesizes Rochester/LCSC distributor pricing, same-family EP910 drop-in alternatives, and practical legacy-design notes not collated in the original Altera datasheet.
EP910PI-35T - 24-Macrocell Classic EPLD, 35ns, PDIP-40 | Altera
The Altera EP910PI-35T is a member of the Classic EPLD (Erasable Programmable Logic Device) family, a 24-macrocell CMOS PLD with a 35ns pin-to-pin logic delay and a 28.6 MHz counter frequency, supplied in a 40-pin Plastic DIP (PDIP) package with a 5V supply and TTL-compatible I/O. A Classic EPLD is an electrically erasable programmable logic device that preceded modern CPLDs, integrating multiple PAL/GAL-type functions into a single CMOS IC. The Classic family hierarchy sits within Erasable PLD -> PLD -> Programmable Logic -> Digital Logic IC -> Semiconductor, providing glue-logic integration, bus decoding, and state-machine consolidation in systems built before low-cost FPGAs dominated the market. The EP910 integrates 24 macrocells across 450 usable gates, supports 100% TTL emulation, and includes on-board logic test circuitry for AC specification verification during production. The device is reprogrammable via UV erasure, supports 5V VCC operation, and exposes JTAG-like boundary-scan testability in higher-grade variants. Architecture features a global interconnect matrix, 24 product-term-driven flip-flop macrocells, and pin-to-pin delays as fast as 35ns for the -35 speed grade. Typical applications include address decoding for 8-bit/16-bit microprocessor systems, glue-logic consolidation in legacy industrial controllers, state-machine implementation in test equipment, and bus-interface bridging between asynchronous peripherals. The wide 5V tolerance and 100% TTL emulation make it well suited to replace discrete 74LS/74F logic on legacy boards without level-shifting. When designing with this device, ensure the 5V supply is well decoupled with 0.1uF ceramic capacitors placed within 5mm of the VCC and GND pins, and reserve the global clock pin for high-frequency synchronous logic to minimize skew. Inputs exceeding VCC by more than 0.5V should be clamped, since EP910 outputs drive TTL but the input structures are CMOS. This page synthesizes distributor pricing, pin-compatible Classic EPLD drop-in alternatives, and practical design notes not aggregated on any single manufacturer or distributor product page, providing engineering value beyond the datasheet PDF alone.
EP910PI-40 - 24-Macrocell Classic EPLD, 43ns, PDIP-40 | Altera
The Altera EP910PI-40 is a 24-macrocell Classic EPLD from the EP910 family, fabricated on an advanced low-power CMOS process and packaged in a 40-pin PDIP (PI) through-hole format. It integrates 24 macrocells interconnected via a global programmable interconnect, with 12 dedicated inputs and 24 I/O lines, supporting a maximum clock frequency of 25 MHz and a propagation delay of 43 ns (the "-40" speed grade). According to Altera's EP910 datasheet, the device is specified for commercial operation with a 4.75 V to 5.25 V single 5 V supply and is part of the legacy Classic EPLD family. What is an EPLD? An Erasable Programmable Logic Device (EPLD) is a non-volatile programmable logic device that uses UV-erasable CMOS technology. It sits in the hierarchy between simple PLAs/PALs and modern FPGAs/CPLDs, providing deterministic pin-to-pin logic timing, low power consumption, and in-system reprogrammability via an external EPROM programmer. Classic EPLDs like the EP910 were widely used in the late 1980s and 1990s as glue logic, bus interface controllers, and state-machine replacements for 7400-series TTL, with PAL-type macrocell architecture optimized for high-speed combinatorial and registered logic. Key features of the EP910PI-40 include a PAL-type macrocell architecture, 24 macrocells, 12 dedicated inputs, 24 bidirectional I/O lines, 2 external clock inputs, and a tPD of 43 ns (commercial speed grade 40). The device supports both combinatorial and registered logic with user-configurable output polarity, and offers programmable I/O architecture with three-state output control. The CMOS process delivers low power consumption compared to bipolar PAL alternatives of the same era. Typical applications include legacy TTL/CMOS glue-logic replacement, address decoding for microprocessor systems, bus-interface and arbiter logic, state-machine implementation for industrial controllers, and as a pin-compatible replacement for several bipolar PAL devices. Designers migrating from bipolar PALs benefit from reduced power, reprogrammability, and improved design security. According to distributor data, this part remains in active production via Rochester Electronics as a long-term support device. When designing with this part, note that the EP910PI-40 requires a 5 V supply, programming via a legacy Altera programming hardware (such as the A+PLUS or MAX+PLUS baseline tools), and that the -40 speed grade is the slowest in the EP910 family. For new designs, designers should evaluate whether a modern CPLD (e.g., MAX V family) offers better cost, power, and toolchain support, but for legacy systems requiring exact drop-in replacement of installed EP910 hardware, the PI-40 remains the canonical part. This page synthesizes distributor pricing from Jotrin, Octopart, and Rochester Electronics, drop-in alternatives across the EP910 speed-grade family, and practical design notes not found in the original manufacturer datasheet.
EPC1441PCB - Altera Enhanced Configuration Device for SRAM FPGAs
The Altera (Intel) EPC1441PCB is an Enhanced Configuration Device (PLCC-20 package) designed as a single-chip, high-speed configuration solution for very high-density SRAM-based FPGAs. It provides non-volatile storage and a controller that loads the FPGA configuration bitstream at power-up via the Altera serial or parallel configuration bus. The device supports ACEX 1K, APEX 20K, APEX II, FLEX 10K, FLEX 6000, FLEX 8000, and Mercury FPGA families, replacing older discrete PROM/EPROM + microcontroller solutions with a single 20-pin PLCC package. A configuration device is a non-volatile memory plus controller IC used to bootstrap SRAM-based FPGAs at power-on. SRAM FPGAs (such as Altera FLEX and APEX series) lose their configuration when power is removed, so they must be loaded from external non-volatile storage on every boot. The configuration device family sits in the boot hierarchy between the power supply, the FPGA, and the JTAG chain, providing a fast, in-system programmable configuration source. EPC1441PCB belongs to the Altera enhanced configuration family, which supersedes the older EPC1 and EPC2 devices by adding in-system programmability, faster configuration times, and higher density. Key features include 4,435,200 bits (approximately 4 Mb) of on-chip flash memory, in-system programmability via JTAG, automatic configuration of FPGAs at power-up, 3.3V core operation with 5V-tolerant I/O, and a 20-pin Plastic Leaded Chip Carrier (PLCC-20) package. The device uses a 4-pin Altera configuration interface (nSTATUS, nCONFIG, DCLK, DATA) for FLEX/ACEX series and adds CONF_DONE signals for APEX support, simplifying board layout. Operating temperature range is commercial 0C to +70C with low standby current suited for power-aware designs. The EPC1441PCB integrates a flash memory array, a configuration controller, and JTAG/IEEE 1149.1 boundary-scan logic on a single die. The controller handles bitstream decompression, error detection, and the serial/parallel handshake with the target FPGA, freeing the host processor from any boot-time intervention. The 4 Mb density supports full-configuration of medium-to-large Altera FPGAs such as APEX 20K200E and FLEX 10K100A without external storage. Typical applications include industrial control boards using FLEX 10K, communication line cards based on APEX 20K, test-and-measurement instruments built on ACEX 1K, and legacy replacement of older EPC2-based designs. The 4 Mb density makes it suitable for APEX 20K and FLEX 10K devices of moderate logic capacity. The PLCC-20 socket-friendly package is convenient for through-hole prototypes and field-serviceable systems. When designing with EPC1441PCB, place a 0.1 uF decoupling capacitor close to VCC and observe the 3.3V supply tolerance; 5V-only rails require a level shifter. JTAG chain ordering should place the configuration device first when multiple devices share the bus, and unused CONF pins must be left open per Altera application notes. This page synthesizes distributor pricing, package-level drop-in alternatives from the same Altera Enhanced Configuration family, and practical design notes not found in the original datasheet.