LPC804M101JHI33Y Complete Guide: 32-bit Cortex-M0+ MCU Specs, Pinout, Alternatives and Sourcing

Quick Answers

The NXP LPC804M101JHI33Y is an active-lifecycle, surface-mount 32-bit ARM Cortex-M0+ microcontroller in a 32-pin HVQFN (5x5 mm) package, integrating 32 KB of flash memory, 4 KB of SRAM, and a maximum CPU clock of 15 MHz. The part combines a 12-bit ADC, a 10-bit DAC, an analog comparator, a capacitive touch interface, and a programmable logic unit (PLU) with two I2C ports, one SPI bus, and up to two USARTs, all operating from a 1.71 V to 3.6 V supply across -40 °C to +105 °C. As of 2026-10-06, the LPC804M101JHI33Y is priced at $0.78 per unit at 3,000-piece reels, with 99,999 units listed in distributor stock and a minimum order quantity of 1. The MCU is supported by NXP's MCUXpresso SDK and targets IoT sensor nodes, capacitive touch user interfaces, LED lighting controllers, battery-powered medical accessories, and small-appliance white-goods control. Engineers and buyers evaluating this part can review detailed specifications on the LPC804M101JHI33Y product page or browse the full XAIPART component catalog for sourcing options.

Technical Guide

What is the right way to design in the LPC804M101JHI33Y?

The LPC804M101JHI33Y fits designs that outgrow 8-bit microcontrollers but do not justify the BOM cost of Cortex-M3/M4 silicon. The 15 MHz Cortex-M0+ core delivers deterministic single-cycle GPIO access, the 32 KB flash holds a small RTOS or state machine, and the 4 KB SRAM provides zero-wait-state execution at 15 MHz. Engineers typically deploy this part for sensor-hub firmware, capacitive touch remotes, low-cost HID bridges, and small motor-control loops. Begin the schematic capture with the SWD debug path, the power network, and the analog reference decoupling before laying out the rest of the board, and confirm the SWD connector placement against the planned enclosure.

How should the power network be laid out for low ADC noise?

The supply network uses a single 1.71 V to 3.6 V rail feeding VDD (pin 7) and VDDA (pin 27), with VSS (pin 8) and VSSA (pin 28) returning to a clean analog ground. To keep the 12-bit ADC noise floor at usable levels, decouple VDD with a 100 nF X7R ceramic placed within 2 mm of the pin, and add a 1 µF bulk capacitor at the regulator output. When the digital rail carries switching currents above 10 mA, ferrite-bead-isolate VDDA from VDD; below 5 mA they may be tied directly. The analog comparator input on pin 29 and the 10-bit DAC output on pin 30 must not be adjacent to switching DC-DC nodes or PWM traces on inner PCB layers, and the analog ground pour should extend under both pins before stitching back to VSS.

How is the SWD debug path routed?

The SWD debug pins are PIO0_1/SWDIO (pin 10) and PIO0_2/SWCLK (pin 11). Route both to a standard 10-pin Cortex Debug connector with 100 Ω series resistors or ferrite beads on long traces. Leave 4.7 kΩ pull-ups on SWDIO and SWCLK if the connector is not populated in production. The reset pin PIO0_0/RESET (pin 9) should carry a 10 kΩ pull-up and a 100 nF decoupling cap to VSS. Engineers using long flying leads from the probe should add a TVS diode array on SWDIO and SWCLK to survive ESD events during rework, and avoid running the SWD traces parallel to switching signals for more than 10 mm.

How is the capacitive touch interface used?

The capacitive touch interface uses dedicated Cap Touch channels on PIO0_8 (pin 17) and PIO0_9 (pin 18). NXP's royalty-free capacitive touch library handles charge/discharge timing, and the PLU can wake the Cortex-M0+ core from deep sleep on a touch event without the CPU being clocked. Keep touch sensor traces short, guarded to ground, and overlaid with a 1 mm to 3 mm dielectric cover (typically ABS or glass). For sliders, use a ladder of two to four Cap Touch channels; for matrix touch, multiplex additional GPIO through external diodes. Avoid placing the touch sensor traces near switching nodes such as DC-DC inductors or PWM-driven LEDs, and route the sensor traces on a layer that does not cross return currents from digital signals.

What firmware architecture fits 32 KB flash and 4 KB SRAM?

The 32 KB flash holds a CMSIS-RTOS RTX configuration, a state machine, or a bare-metal loop with IAP bootloader. Reserve at least 8 KB for the bootloader and 4 KB for the application, leaving 20 KB for application code. The 4 KB SRAM fits sensor FIFO arrays, HID report buffers, or a small protocol stack. Use the on-chip CRC engine to verify boot images before jumping into the application, which is required for IEC 60730-class firmware integrity on white-goods designs. NXP's MCUXpresso SDK ships CMSIS-DSP and CMSIS-RTOS2 libraries sized for these memory budgets and validated on the LPC804M101JHI33Y silicon, and the LPCXpresso IDE integrates GCC and flash programming in a single toolchain.

How is the Programmable Logic Unit used as glue logic?

The PLU replaces external AND/OR gates by mapping Boolean expressions to internal LUTs. A typical use case is waking the MCU on a touch event while the CPU is in deep-sleep: the PLU monitors the Cap Touch comparator output and asserts an interrupt. This keeps standby current under 1 µA on a coin cell, critical for battery-powered remote controls and wall-switch sensors. The PLU is configured through the MCUXpresso SDK's PLU driver and retains its wiring across deep-sleep resets. Compared with a discrete logic IC, the PLU removes BOM cost and PCB area while improving EMI immunity, and engineers can change the glue logic in firmware rather than re-spinning the board.

How is the SWD debug path preserved in production?

In production firmware, retain SWD access through a 2x5 1.27 mm header or test-pad access to PIO0_1 and PIO0_2. Disable the SWD pins as GPIO only after the bootloader confirms secure firmware and lock the debug port via the CRP (Code Read Protection) word at flash offset 0x0000 02FC. Engineers must balance field-updatability against IP protection; NXP's UM11041 application note covers the CRP options in detail. For small-volume white-goods designs, leaving SWD accessible via pogo-pin test pads avoids depopulating the connector on every unit and supports field firmware updates during the warranty period.

What communications peripherals are exposed?

The part exposes two I2C interfaces (PIO0_21 is shared with I2C SDA on pin 4), one SPI interface, and up to two USARTs. The two I2C buses allow simultaneous connection of a sensor front-end and a wireless module such as the NXP OL2351. The single SPI bus supports up to four slave selects through GPIO muxing for addressable-LED strings or external flash. The two USARTs can drive a main display and a service-diagnostic port on white-goods control boards simultaneously. The CRC engine on-chip accelerates packet validation for I2C and SPI traffic, offloading the 15 MHz Cortex-M0+ core from per-byte checksum work.

What timing resources are available?

The multi-rate timer (one instance) and the self-wake-up timer handle PWM generation, event timing, and low-power wake-ups. The multi-rate timer repeats at programmable intervals from microseconds to seconds, suitable for LED dimming curves and sensor sampling. The self-wake-up timer keeps time in deep-sleep and resets the Cortex-M0+ core at a programmed interval. Together with the PLU, these timers let the MCU stay in deep-sleep for 99 percent of its duty cycle in battery-powered designs, with the multi-rate timer triggering the ADC sample and the self-wake-up timer scheduling the next radio transmission.

Alternatives & Comparison

What drop-in alternatives exist within the NXP LPC80x family?

Three parts in the LPC80x family share the 32-HVQFN (5x5 mm) footprint with the LPC804M101JHI33Y: the LPC802M011JHI33 (16 KB flash, 2 KB SRAM, no capacitive touch, no PLU), the LPC804M001JHI33 (same die and package, lower-flash variant per the NXP LPC80x family), and the LPC804M101JHI33E (same die and package, extended temperature range). Footprint compatibility means existing PCB layouts do not require rework when migrating within the family, and the SWD debug connector placement is preserved across all four parts.

Summary: The LPC802M011JHI33 drops to 16 KB flash and 2 KB SRAM and removes the capacitive touch interface and PLU. It is the right drop-in for designs that do not need touch sensing and fit in 16 KB of code. The LPC804M001JHI33 is the lower-flash sibling in the same package, while the LPC804M101JHI33E offers identical peripherals with an extended temperature range for harsher environments. For cross-vendor migration, the STM32G031G8U6 uses a QFN-28 or TSSOP-28 footprint that does not match the LPC804M101JHI33Y's 32-pin HVQFN; PCB rework is required and the migration is not drop-in. Designers evaluating alternatives can compare the LPC804M101JHI33Y against the ATMEGA3209-AU 8-bit megaAVR MCU when stepping up from an 8-bit architecture, or read about managed-ethernet silicon in the KSZ9893RNXI Gigabit Ethernet switch guide.

Industry Insight

What is the supply and lifecycle situation as of 2026-10-06?

The LPC804M101JHI33Y carries an active lifecycle status from NXP Semiconductors, meaning the part is in full production and not subject to last-time-buy notices. Distributor stock is listed at 99,999 units, providing multi-program visibility for prototype and small-volume production runs. Pricing as of 2026-10-06 spans six verified tiers: $1.65 at 1 piece, $1.48 at 10 pieces, $1.22 at 100 pieces, $1.05 at 500 pieces, $0.92 at 1,000 pieces, and $0.78 at 3,000 pieces. The MOQ of 1 allows engineers to order single pieces for engineering samples and breadboard prototypes without committing to a full reel. Procurement teams evaluating this MCU for long-life products should track NXP's product longevity program and confirm that the LPC80x family is covered for the target production horizon, typically ten years for industrial white goods and five years for consumer electronics.

How does this part fit into the broader MCU market?

Within the Cortex-M0+ tier, the LPC804M101JHI33Y sits between bare-bone 8-bit replacement MCUs and richer Cortex-M0+ parts such as the LPC844M201JHI33 (which adds USB and SCTimer/PWM on a 64 KB flash budget). The 32 KB flash and 4 KB SRAM combination is the practical minimum for capacitive touch firmware plus bootloader, and the PLU is the differentiator against competitors that lack configurable glue logic. The 32-HVQFN (5x5 mm) package is mainstream in the industry, ensuring second-source assembly and rework capability at most contract manufacturers. Combined with the active lifecycle status and large stock pool, the LPC804M101JHI33Y is a low-risk choice for cost-sensitive industrial and consumer designs. Buyers can review current stock and tier pricing on the LPC804M101JHI33Y product page or compare it with related parts in the XAIPART catalog, and deeper design articles are available on the XAIPART blog.

Trends & Outlook

What should buyers and engineers watch on the LPC804M101JHI33Y?

Three trends matter for sourcing and design teams working with this part. First, the 32 KB flash and 4 KB SRAM ceiling is well below the 64 KB and 128 KB flash tiers common in newer Cortex-M0+ parts. Buyers planning firmware growth above 32 KB should plan a migration path now, even if the current design fits within the verified memory budget. Second, the 1.71 V minimum operating voltage allows direct Li-ion or coin-cell operation, removing an external LDO and reducing BOM cost by USD 0.10 to USD 0.20 per board — a margin advantage that is amplified at 3,000-piece reels priced at $0.78 per unit as of 2026-10-06. Third, the on-chip PLU and capacitive touch interface continue to differentiate the LPC80x family from general-purpose Cortex-M0+ competitors, and engineers should leverage these peripherals to displace external glue-logic ICs and dedicated touch ICs, with the application notes citing up to USD 0.40 per board savings when the PLU replaces discrete logic.

How does the LPC804M101JHI33Y compare to the wider Cortex-M0+ market?

The STM32G030K8T6 from STMicroelectronics targets the same low-cost market segment and delivers roughly 4x the CPU performance at 64 MHz with 64 KB flash. Engineers who need headroom for higher MIPS or more code should consider the STM32 part, accepting that the LPC804M101JHI33Y still wins on PLU integration and on NXP's MCUXpresso toolchain. For step-up within the NXP portfolio, the LPC844M201JHI33 adds USB and 64 KB flash for designs that have outgrown 32 KB. For step-up within 8-bit architectures, the ATMEGA3209-AU offers IEC 60730 FuSa support for safety-critical applications. Designers building high-speed wired interfaces can also reference the KSZ9893RNXI Gigabit Ethernet switch guide for managed-switch designs that pair with Cortex-M0+ host controllers, and the AP63205WU-7 sync buck converter guide for the 1.71 V to 3.6 V rail design.

What design decisions should be locked before commit?

Engineers should design the SWD debug header into the first prototype spin, even if field firmware updates are not planned today, because rework on a 32-pin 0.5 mm pitch HVQFN package is impractical without a rework station. Confirm that the chosen firmware configuration fits in 32 KB of flash after including the bootloader, RTOS, and capacitive touch library; if not, the LPC844M201JHI33 (64 KB flash) or the STM32G030K8T6 (64 KB flash, 64 MHz) are sensible stepping stones within their respective ecosystems. Lock the operating temperature grade early: the standard part spans -40 °C to +105 °C, and the LPC804M101JHI33E variant extends this for harsher industrial environments. Finally, validate the 1.71 V minimum supply against the lowest expected battery voltage under load, including a margin of 50 mV to 100 mV to absorb transient drops during peak transmit currents, and confirm that the chosen sensor front-end, wireless module, and indicator LEDs do not push the I/O count above the 30 general-purpose pins available on this 32-HVQFN package.