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পণ্য (120+)
UCD90160ARGCT - 16-Rail PMBus Sequencer & Monitor | Texas Instruments
The Texas Instruments UCD90160ARGCT is a 16-rail PMBus/I2C addressable power supply sequencer and system health monitor with ACPI support, housed in a 64-pin VQFN (RGC) 9x9 mm package. It samples all 16 voltage rails every 400 µs using a 12-bit ADC with a 2.5 V, 0.5% internal reference, supports up to four programmable undervoltage and overvoltage thresholds per monitor, and operates from a 3 V to 3.6 V supply with typical quiescent current of 50 mA. A power supply sequencer is a programmable controller that supervises the turn-on and turn-off order, voltage margin, and fault response of multiple DC rails in a complex system such as a server, FPGA SoM, or ATX-class board. By centralizing rail sequencing in one IC rather than discrete reset supervisors, designers replace glue logic, RC delay chains, and multiple supervisor ICs with one PMBus-programmable device, simplifying BOM and improving diagnostic visibility through the integrated system health telemetry interface. Key features include sequence control based on time, rail-dependency, and pin-dependency, ACPI support for desktop power-button S0/S3/S5 state coordination, a 100-pin-compatible scalable family (UCD90120A / UCD90124A / UCD90910 / UCD90160), and integration with the TI Fusion Digital Power Designer GUI. Black-box fault logging, margining, and closed-loop trim of downstream DC/DC converters are standard capabilities supported through the PMBus command set. The device integrates a 12-bit ADC and precision reference, fault-logging non-volatile memory, programmable GPIOs for PERST#, ENABLE, and PG_OUT behavior, and a JTAG/I2C/PMBus host interface. The architecture follows the UCD90xxx family: an embedded microcontroller runs sequencing state machines while a dedicated ADC front-end maintains 400 µs rail sampling independent of host interaction. The result is deterministic rail sequencing even when the system host is stalled during fault recovery. Typical applications include ATX/Server power sequencing for multi-rail processors, FPGA and SoC power-up coordination, industrial and telecommunications equipment with hot-swap controllers, and automated test platforms that require precise rail ordering and margin verification. ACPI support makes the part particularly natural in x86 system designs that need S3 suspend/resume state transitions. When designing with this device, plan for a 3.3 V auxiliary rail present at all times because the sequencer must remain alive before the main rails come up. Place the decoupling capacitor network (1 µF + 0.1 µF) within 5 mm of the AVDD pin and follow TI's RGC PCB layout guideline in the EVM user's guide to keep ADC readings clean across all 16 channels. This page synthesizes distributor pricing, drop-in cross-reference parts, and practical layout notes compiled from the manufacturer datasheet and TI EVM user's guide so engineers can quickly qualify the UCD90160ARGCT against alternative sequencers in the same package family.
UCD90320ZWST - 32-Rail PMBus Power Sequencer & System Manager | TI
The Texas Instruments UCD90320ZWST is a 32-rail PMBus-addressable power sequencer and system manager housed in a 169-ball NFBGA package measuring 12 mm x 12 mm with a 0.8 mm ball pitch. The device integrates 24 ADC channels (AMONx) that monitor power supply voltage, current, and temperature, plus 84 GPIO pins that can be configured as 8 digital monitors (DMONx) and additional general-purpose I/O. It supports sequencing, margining, and supervising up to 24 voltage rails plus 8 digital rails in complex multi-rail systems such as FPGA, ASIC, and processor power trees. A power sequencer is a specialized supervisory IC that orchestrates the turn-on/turn-off order, timing, and fault response of multiple voltage rails. In the hierarchy of power-management ICs, sequencers sit above simple voltage supervisors (single-rail reset/watchdog) and below PMBus-configurable digital power controllers. They translate high-level system events into coordinated rail-by-rail actions using logic expressions, timers, and PMBus commands. The UCD90320 adds closed-loop monitoring, fault logging, and non-volatile configuration to that role. Key features include flexible sequence-on and sequence-off dependencies based on delay time, Boolean logic, and GPIO triggers; full OV/UV/OC/UC/temperature/time-out/GPI-triggered fault detection; pin-selected rail states for up to 8 user-defined power states using 3 GPIs (supporting ACPI low-power modes); cascade-capable FAULT pin for synchronized fault responses across multiple devices; and on-chip non-volatile memory for configuration storage. The PMBus interface supports standard command set plus TI extensions for sequencing and fault response. Architecturally, the UCD90320 combines a Cortex-M0-class configuration manager with a 24-channel sigma-delta ADC front end, a dedicated sequencing state machine, and an I2C/PMBus slave interface. The 0.8 mm-pitch BGA supports the high pin count required for 24 analog inputs, 84 GPIO, and PMBus/serial interface pins in a compact 12x12 mm outline. Typical applications include FPGA/ASIC power-rail sequencing and supervision, ATCA/telecom board power management, server and storage-system boot sequencing, industrial multi-rail power distribution, and ACPI-compliant low-power state coordination. Use the UCD90320 Fusion Digital Power Designer GUI for offline configuration and the TI USB-to-GPIO adapter for in-system programming. When designing, always allocate sufficient bulk capacitance on monitored rails and verify ADC input dividers against the 6 V full-scale range.
UCD9090 - 10-Rail Power Sequencer & Monitor | Texas Instruments
The Texas Instruments UCD9090 is a 10-rail PMBus/I2C addressable power-supply sequencer and monitor. It integrates a 12-bit ADC for monitoring up to 10 power-supply voltage inputs, and 23 GPIO pins can be used for power-supply enables, power-on reset signals, external interrupts, cascading, or other system functions. Ten of these pins offer PWM functionality, enabling flexible control of power rails. The device is available in a 48-pin VQFN (7x7) package, suitable for compact board designs. A power-supply sequencer and monitor is a specialized power management IC that controls the order in which multiple voltage rails are turned on and off during system startup and shutdown. This is critical in complex electronic systems where certain rails must be established before others to prevent latch-up, excessive current draw, or damage to sensitive components. The UCD9090 sits within the power management IC hierarchy, specifically under the category of sequencers and monitors, which are essential for reliable multi-rail power delivery in servers, networking equipment, and industrial systems. Key features of the UCD9090 include its 10-channel sequencing capability, 12-bit ADC for accurate voltage monitoring, and PMBus/I2C interface for configuration and telemetry. The device supports ACPI (Advanced Configuration and Power Interface) for advanced power management in computing systems. Its GPIO pins provide versatile control options, including PWM outputs for margining or dynamic voltage scaling. The UCD9090 is designed for high-reliability applications, with a wide operating temperature range and robust fault handling. Technically, the UCD9090 uses a digital state machine to manage sequencing sequences, which can be programmed via PMBus commands. The integrated ADC samples each rail's voltage and compares it against programmable thresholds, triggering faults if voltages exceed or fall below limits. The device can also log fault events and report them to a host controller. This architecture enables precise, repeatable power sequencing and monitoring, reducing the need for external supervisory circuits. Typical applications include server and storage systems, networking equipment, telecommunications infrastructure, and industrial control systems. In these applications, the UCD9090 ensures that power rails are sequenced correctly, preventing system failures and improving reliability. Its PMBus interface allows for real-time monitoring and control, making it ideal for systems that require dynamic power management. When designing with the UCD9090, it is important to configure the sequencing parameters and fault thresholds via PMBus to match the specific power-up requirements of the system. Proper decoupling and layout are essential to ensure accurate ADC readings and stable operation. The device's flexibility in GPIO assignment should be leveraged to optimize board layout and minimize signal routing complexity.
UCD9090RGZ - 10-Rail Sequencer/Monitor, 48-VQFN | Texas Instruments
The Texas Instruments UCD9090RGZ is a 10-rail PMBus/I2C-addressable power-supply sequencer and monitor with ACPI support, housed in a 48-pin VQFN (RGZ) package (7x7 mm). It integrates a 12-bit ADC that samples up to 10 voltage rails and eight general-purpose digital inputs (GPIs), making it a system-health monitoring companion for multi-rail designs based on point-of-load converters. A power supply sequencer is a dedicated supervisory IC that turns rails on and off in a defined order, monitors their health after start-up, and reacts to faults. In the broader hierarchy it sits between the PMBus-controlled point-of-load (POL) converters it commands and the system-level power management firmware running on the host. Devices such as the UCD9090RGZ replace discrete supervisory chains with a single programmable, telemetry-rich block that designers can reconfigure over PMBus without a board spin. Key features include per-rail margining, programmable under-voltage and over-voltage thresholds, fault logging in non-volatile memory, watchdog timer, and pin-selected low-power states via up to three GPIs (eight ACPI-style states). The on-board 2.5 V, 0.5% internal reference gives repeatable ADC-based rail measurements, while the 12-bit ADC provides 0.1% typical resolution across the 0 V-2.5 V range. ACPI support lets the device implement S0/S1/S3/S4/S5-style low-power modes for energy-aware systems. Architecturally, the UCD9090RGZ pairs an internal ARM7-class controller with the sequencer/monitor state machine. The host configures rails via PMBus commands; the on-chip sequencer then drives external PGOOD/ENABLE/MARGIN pins and reads back rail voltages through the muxed ADC. The 48-VQFN (RGZ) package provides adequate thermal headroom for the 3.3 V supply operation. Typical applications include FPGA/processor power sequencing in telecom and networking line cards, ATCA/AMC/ATX power rails in servers, industrial PLCs with multiple voltage domains, and any system requiring ACPI-style sleep state coordination. The UCD90SEQ48EVM-560 evaluation module accelerates bring-up using the UCD9090RGZ on a 48-pin socketed board with USB-to-PC GUI. When designing with this part, place the device close to the regulators it sequences to minimize the loop on the EN/MARGIN/PGOOD traces, and follow TI's recommended BUF layout for the 0.1 uF/1 uF/10 uF decoupling. The fault log, programmable GPI de-bounce, and per-rail fault-response policy should be configured in the Fusion Digital Power Designer GUI before production. This page consolidates distributor pricing, drop-in alternatives, and design notes not bundled into the manufacturer datasheet, giving engineers a faster path from selection to bring-up.
X5043M8I-2.7A - CPU Supervisor w/ 4K SPI EEPROM | Renesas
The Renesas (formerly Xicor / Intersil) X5043M8I-2.7A is a single-chip CPU supervisor that integrates four critical system functions into one 8-pin MSOP/TSSOP device: power-on reset control, a watchdog timer, supply voltage supervision, and a 4 Kbit block-locked serial EEPROM with an SPI interface. It provides 1 voltage monitor with a factory-trimmed threshold in the 2.7 V family, an active-low reset output in open-drain configuration, and a guaranteed minimum reset timeout of 100 ms. A CPU supervisor (also called a voltage supervisor or reset IC) is a dedicated power-management device that protects a microcontroller, ASIC, or DSP from the brown-out, power-glitch, and firmware-hang conditions that firmware alone cannot detect. Within the broader taxonomy it sits under supervisor and reset IC -> power management IC -> mixed-signal semiconductor. The supervisor's role in a system is to assert a deterministic reset until the supply rail is stable and within tolerance, then continue to monitor VCC and to service a watchdog window that proves the host CPU is still executing valid code. Key features include low VCC operation down to 1 V to support battery-backup EEPROM write, an internal oscillator that removes the need for an external timing component, hardware block-lock protection for the upper half of the EEPROM array via the WP pin, and selectable watchdog timeout options. The SPI serial interface runs at clock rates up to several MHz, suitable for firmware-parameter storage, board-strapping, and calibration tables. The integrated design reduces board area, BOM count, and software overhead compared with discrete supervisor + EEPROM solutions. The architecture combines a precision bandgap reference, a comparator chain for VCC monitoring, a watchdog counter clocked from an internal oscillator, and a high-EEPROM cell array accessed through a standard SPI slave port. The I2C-style three-wire interface uses SCLK, SO, SI, and CS, with the WP input gating writes to the protected memory quadrant. Typical applications include microcontroller reset and parameter storage in industrial controllers, secure boot sequencing in embedded modules, watchdog supervision in motor drives, and EEPROM-backed event logging in metering equipment. Designers choose the X5043M8I-2.7A when a 2.7 V-class reset threshold is required and a small MSOP-8 footprint is mandated. A key design consideration is decoupling: place a 0.1 uF bypass capacitor close to VCC, and observe the CS setup/hold timings for reliable SPI communication at maximum clock rates. The reset pin is open-drain and requires an external pull-up resistor. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the bare manufacturer datasheet.
X5325S8IZ-4.5A - CPU Supervisor with 32K SPI EEPROM, 4.5V | Renesas
The Renesas X5325S8IZ-4.5A is a CPU Supervisor with 32 kBit SPI EEPROM that integrates four essential system-management functions into a single 8-pin SOIC package: power-on reset control, programmable watchdog timer, supply voltage supervision, and block-lock-protected serial EEPROM memory. It is specified for a 4.5 V VCC trip threshold (VCC tolerance +/-10%), operates over the standard industrial temperature range, and offers an active-high reset output (RST) suitable for monitoring 5 V system rails. A CPU Supervisor (also called a voltage supervisor, reset IC, or power-supply monitor) is a mixed-signal IC that safeguards a microcontroller, microprocessor, or DSP by monitoring its supply rail and asserting a reset during brown-out, power-up, and power-down events. This category sits within the PMIC (Power Management IC) hierarchy: supervisor -> PMIC -> power management -> semiconductor. By combining an EEPROM with the supervisor, the X5325 reduces part count, board area, and BOM cost in designs that otherwise need a standalone EEPROM for configuration, calibration, or parameter storage. Key features include a precision VCC voltage detector with 4.5 V nominal trip point, a programmable watchdog timer with selectable time-out, an open-drain / open-collector reset output, SPI (Serial Peripheral Interface) bus access up to 5 MHz for the 32 kbit (4 kbyte) EEPROM, and software-controllable block-lock protection that prevents accidental writes to protected memory regions. The Z suffix indicates the Pb-free (lead-free) finish and the I suffix denotes the industrial temperature grade (-40 C to +85 C). Internally, the X5325S8IZ-4.5a pairs an analog voltage reference and comparator (for VCC monitoring) with a state machine that drives the reset pin and watchdog logic, alongside a separate SPI slave with embedded EEPROM. The 32 kbit EEPROM uses a 4 kbyte organization and supports page-write mode for efficient parameter updates. Block-lock protection prevents rogue firmware from corrupting calibration constants stored in protected sectors, which is critical in safety-relevant designs such as industrial PLCs and appliance controllers. Typical applications include 8051 / ARM Cortex-M0 boot-monitoring in white goods, HVAC controllers, set-top boxes, and any 5 V MCU platform needing tamper-safe parameter storage (e.g., trim settings, serial numbers, runtime hours). The wide VCC tolerance also makes it suitable for 5 V +/-10% industrial 24 V-bus-derived rails. Choose this part when a low-pin-count supervisor plus serial EEPROM in one IC simplifies layout and lowers cost versus a discrete supervisor + standalone EEPROM solution. When designing with this device, place a 0.1 uF decoupling capacitor close to VCC and keep SPI lines short to prevent ringing at 5 MHz. Reset pull-up resistor selection affects rise time - a 10 kohm to 100 kohm range typically balances current draw with rise-time. For in-system EEPROM writes, ensure VCC remains within the data-retention range or block writes with the watchdog-induced reset. This page synthesizes distributor pricing, same-family drop-in alternatives, and practical supervisor design notes not found in the standalone manufacturer datasheet alone.