Video ICs
Products (13)
AD725ARZ - RGB to NTSC/PAL Video Encoder SOIC-16 | Analog Devices
The Analog Devices AD725ARZ is a low-cost, general-purpose RGB-to-NTSC/PAL video encoder housed in a 16-pin SOIC (SO-16) package, converting red, green and blue color component signals into their corresponding luminance (baseband amplitude) and chrominance (subcarrier amplitude and phase) outputs in accordance with either NTSC or PAL broadcast standards. The part is supplied in the ARZ (SOIC, tape-and-reel) grade and is the industry-standard monolithic solution for converting digital RGB or analog RGB video from graphics controllers and framebuffers into composite or Y/C (S-Video) outputs. What is an RGB to NTSC/PAL encoder? An NTSC/PAL encoder is a mixed-signal IC that accepts red, green and blue (RGB) video data — either as analog voltages or digital codes — and synthesizes a composite analog video waveform conforming to the NTSC (M/NTSC, 525-line, 60 Hz) or PAL (625-line, 50 Hz) broadcast standard. The encoder sits in the analog signal chain between the source (graphics controller, video DAC, framebuffer) and the display or modulator (TV, modulator, capture card). In the broader IC hierarchy, the AD725 belongs to the video encoder / video DAC family, itself a sub-category of display drivers and serializer ICs. Key features include integrated luma (Y) and chroma (C) outputs, on-chip subcarrier generation, an integrated luma trap port for clean composite video, and a TTL-compatible digital interface for input format selection. The AD725 supports both NTSC-M and PAL-B/D/G/H/I/M/N standards with simple mode strapping, eliminating external modulator hardware. Operating from a single +5 V analog supply with low power dissipation, it requires only a handful of bypass components and a 28.63636 MHz (NTSC) or 26.84325 MHz (PAL) crystal. Architecturally, the AD725 uses a current-output DAC topology with internal bandgap references and switched-capacitor filtering, allowing direct connection to 75 ohm video loads with minimal external components. The luma trap output and chroma output are derived from the same RGB input through an internal color-space conversion matrix and subcarrier modulator. Typical applications include set-top box composite video outputs, video game consoles, surveillance DVRs with analog outputs, legacy industrial video overlay boards, and RGB-to-TV converter dongles. The AD725 is also common in FPGA evaluation platforms requiring analog video output and in low-cost broadcast or test equipment that needs composite NTSC/PAL modulation. Designers should note that the part requires a high-frequency crystal oscillator reference and proper 75 ohm termination at both composite and chroma outputs. Bypass the +5 V supply with a 0.1 uF ceramic capacitor plus a 10 uF tantalum or electrolytic capacitor placed within 5 mm of the supply pin to meet PSRR specifications.
ADV202 - JPEG2000 Video Codec | Analog Devices
The Analog Devices ADV202 is a single-chip JPEG2000 codec targeted at video and high-bandwidth image compression applications. It implements the JPEG2000 (J2K) ISO/IEC 15444-1 image compression standard and provides complete compression and decompression processing on one die. The device operates on rectangular pixel tiles, where a tile may contain a complete image up to the maximum supported size or only part of an image, making it flexible for HD and high-resolution still-image pipelines. The ADV202 is offered in a 144-ball BGA package with surface-mount assembly, and it was formerly branded as the ADV-JP2000. A JPEG2000 video codec is a hardware engine that encodes and decodes images using the wavelet-based JPEG2000 Part 1 standard. Unlike block-based JPEG, JPEG2000 employs a discrete wavelet transform followed by entropy coding to produce scalable, high-quality compressed streams. In a hardware codec such as the ADV202, the wavelet transform engine, entropy codecs, memory controller, and control processor are integrated on-chip, eliminating the need for a host DSP or external compressor in many systems. This is important for bandwidth-limited video links because one chip can compress 720p video or large still-frame imagery into a JPEG2000 stream and decompress it on the receive side. Key features include a dedicated video port with glueless connection to common digital video standards such as 720p, plus programmable framing and validation signals for other high-speed synchronous pixel formats. The entropy codecs support all features of JPEG2000 Part 1 except the optional Maxshift ROI. Patented SURF (Spatial Ultra-efficient Recursive Filtering) technology enables low-power, low-cost implementation. Internally, the ADV202 contains a wavelet transform engine, three entropy codecs, an on-board memory system, and an embedded RISC processor that manages bitstream syntax and host commands. From a system perspective, the ADV202 is a complete JPEG2000 compression/decompression solution. The tile engine accepts rectangular arrays of pixel samples, allowing trade-off between memory usage and image size. Because codec operation is tile-based, extremely large still images can be processed in manageable sections, while video can be streamed tile-by-tile. The embedded RISC processor handles host interfaces and entropy codec coordination, reducing external control complexity. Although the ADV202 is no longer recommended for new designs (NRND), its architecture remains the basis of the ADV212, the manufacturer-specified drop-in replacement, which adds JTAG/BSDL and cuts power by up to 50%. Typical applications include broadcast and professional video systems, medical imaging and diagnostic capture, security and surveillance recording, aerospace and UAV payload compression, industrial machine vision, and remote-sensing image archival. For each application, the ADV202's combination of glueless video input, tile-based JPEG2000 Part 1 processing, and single-chip integration reduces BOM size compared with DSP-plus-software implementations. Designers migrating to the ADV212 retain these system benefits because the footprint and functionality are equivalent. Design consideration: because the ADV202 is NRND, a new layout should target the ADV212. Confirm core and I/O supply voltages, maximum clock, power dissipation, and BGA ball map from the official 40-page datasheet before producing a footprint. Verify legacy firmware command compatibility when swapping an ADV202 for an ADV212 in an existing system.
ADV7343BSTZ - 6-DAC 11-Bit 297 MHz Video Encoder LQFP-64 | ADI
The Analog Devices ADV7343BSTZ is a multiformat high-speed video encoder integrating six 11-bit 297 MHz current-steering DACs in a 64-lead LQFP (10x10 mm) surface-mount package. The device supports composite (CVBS), S-Video (Y/C), and component (YPrPb/RGB) analog outputs from a single 3.3V analog supply and 1.8V digital supply, and accepts 8/16/24-bit digital video input in both SDTV (NTSC/PAL/SECAM) and HDTV (720p/1080i/1080p) formats with 4x/8x/16x oversampling. The encoder includes an internal test pattern generator, 4:2:2 to 4:4:4 upsampler, programmable luma/chroma filters, and CCIR/SMPTE timing generators, and is configured through a standard I2C control port. What is a video encoder? A video encoder is a mixed-signal IC that converts digital video pixel data into analog waveforms suitable for driving displays, broadcast modulators, or back-end video DACs. Within the broader taxonomy, the part is a line of video encoder -> video DAC -> mixed-signal IC -> semiconductor. Video encoders sit between the host graphics or media processor and the analog monitor/RF modulator and are a class of display interface ICs that includes HDMI transmitters, VGA DACs, and composite encoder ICs. The ADV7343 belongs to the high-performance broadcast-grade subclass that integrates multiple DACs and full timing-control logic on-chip. Key features include a 297 MHz pixel clock support enabling 1080p60 component analog output, 75 ohm differential output drive eliminating the need for external line drivers, integrated sub-brightness/contrast/hue/saturation controls in the digital domain, and a hardware low-power sleep mode. The LQFP-64 package is industrial-grade (operating from -40C to +85C) and is drop-in compatible with the ADV7342 and ADV7344 family members. The combination of six DACs and full multiformat support lets a single part replace several single-format encoders in a typical set-top box or DVD/Blu-ray subsystem. The ADV7343 uses an advanced 3.3V CMOS process with on-chip bandgap reference and segmented current-steering DAC architecture to achieve low differential nonlinearity and excellent channel-to-channel matching across all six outputs. Programmable output bandwidth and a built-in PLL reduce BOM by eliminating external clock-recovery components, while the I2C port allows dynamic mode changes, gamma correction, and copy-generation management (CGMS) insertion on the fly. The part is AEC-Q100 capable through the automotive-grade variant (contact ADI for full automotive qualification details) and supports the -40C to +85C industrial temperature range in this -BSTZ package. Typical applications include DVD/Blu-ray players and recorders, HDTV set-top boxes, professional broadcast equipment (HD-SDI to analog bridges), automotive infotainment rear-seat entertainment, video editing/duplication equipment, and graphics cards that need to output analog YPrPb/RGB plus composite simultaneously. The device's six independent DACs allow simultaneous S-Video + component + composite without an external mux. When designing with the ADV7343, ensure that the 3.3V AVDD rail is decoupled with at least 10 uF bulk + 0.1 uF ceramic per pin and that the exposed pad (or lead frame) has a continuous ground pour to meet the 64-lead LQFP thermal resistance. Use a 27 MHz reference clock or feed an external pixel clock; the device will generate all required HSYNC/VSYNC timings internally. This page synthesizes distributor pricing, drop-in alternatives, application circuits, and practical engineering notes not found in the manufacturer datasheet alone, helping procurement and design engineers evaluate the ADV7343BSTZ against modern alternatives.
ADV7391BCPZ-RL - 10-Bit SD/HD Video Encoder | Analog Devices
The ADV7391BCPZ-RL is a low power, chip scale 10-bit SD/HD video encoder from Analog Devices, designed for a wide range of video applications including set-top boxes, video players, and displays. It integrates three 2.7 V/3.3 V 10-bit video digital-to-analog converters (DACs) that support composite (CVBS), S-Video (Y-C), and component (YPrPb) video output formats. The device operates from a 1.71 V to 3.63 V supply and draws only 81 mA, making it suitable for power-sensitive portable and consumer electronics. Housed in a compact 32-lead LFCSP-VQ (5x5 mm) package, the ADV7391BCPZ-RL is optimized for space-constrained designs. A video encoder is an integrated circuit that converts digital video data into analog video signals for display or transmission. In the signal chain, the video encoder sits between a digital video source (such as a video processor, FPGA, or SoC) and the analog display interface (such as composite, S-Video, or component outputs). The ADV7391 belongs to the family of digital-to-analog video encoders, which are essential in applications ranging from consumer TVs to professional video equipment. Its role is to bridge the digital and analog domains, ensuring high-quality video output with minimal artifacts. Key features of the ADV7391BCPZ-RL include support for both standard-definition (SD) and high-definition (HD) video formats, with a maximum DAC sampling rate of 297 Msps. The device provides three 10-bit DACs, enabling simultaneous output of CVBS, S-Video, and component signals. It also includes an on-chip voltage reference and supports both interlaced and progressive scan formats. The low power consumption of 81 mA at 3.3 V makes it an excellent choice for battery-powered devices, while the wide operating temperature range of -40°C to +85°C ensures reliability in industrial environments. From a technical perspective, the ADV7391 utilizes a high-speed digital-to-analog conversion architecture that ensures accurate color reproduction and sharp image detail. The device features a flexible digital interface that supports both 4:2:2 and 4:4:4 YCrCb data formats, as well as embedded synchronization signals. The on-chip PLL allows for precise clock generation, reducing external component count. The ADV7391 is part of a family that includes the ADV7390, ADV7392, and ADV7393, which offer different feature sets and package options, allowing designers to select the optimal part for their specific application. Typical applications for the ADV7391BCPZ-RL include set-top boxes, DVD/Blu-ray players, video game consoles, and digital signage. Its low power consumption and small footprint make it ideal for portable media players and handheld devices. The device is also suitable for automotive infotainment systems, where its wide temperature range and robust performance are critical. When designing with the ADV7391BCPZ-RL, it is important to ensure proper decoupling of the power supply pins and to route the analog video outputs away from digital noise sources. The device requires an external crystal or clock source, and the PCB layout should minimize parasitic capacitance on the DAC outputs to maintain signal integrity.
ADV7391WBCPZ - 10-Bit SD/HD Video Encoder, 32-LFCSP | Analog Devices
The Analog Devices ADV7391WBCPZ is a low-power, chip-scale 10-bit SD/HD video encoder providing three 10-bit high-speed video DACs in a 32-lead LFCSP (5x5 mm) package. According to the Analog Devices product page, this encoder accepts SD and HD digital video inputs and supports composite (CVBS), S-Video (Y-C), and component (YPbPr/RGB) analog outputs, making it suitable for set-top boxes, video players, and professional displays. An SD/HD video encoder is a mixed-signal IC that converts digital video data (typically from an MPEG decoder, FPGA, or media processor) into analog baseband signals that drive legacy television inputs, broadcast equipment, and industrial video displays. Within the broader signal chain hierarchy - video processor > video encoder > video DAC > analog video output - the ADV7391WBCPZ integrates the encoder function with on-chip 10-bit DACs, eliminating the need for external video DACs and reducing PCB area. Three integrated DACs are required because component video (YPbPr or RGB) needs three simultaneous analog channels. Key specifications highlighted in the product page and distributor listings include three integrated 10-bit video DACs, support for SD (NTSC/PAL/SECAM) and HD (720p, 1080i, 1080p at reduced DAC speeds) video standards, an operating voltage down to a single 1.8V digital/3.3V analog supply, and a small 32-lead LFCSP footprint rated for the industrial temperature range. The chip-scale 5x5 mm package also exposes a thermal pad for improved heat dissipation in enclosed chassis. The encoder core uses a high-speed digital video input port (typically 8/16/24-bit ITU-R BT.656 / SMPTE 274M / 296M) and on-chip PLL to derive pixel clocks, color subcarrier, and HD sample rates from a single reference. Integrated low-pass reconstruction filters remove DAC image frequencies without external components, simplifying the analog output network to a few series resistors and an output coupling capacitor. Typical applications include set-top box (STB) HDMI-to-analog output back-ends, Blu-ray/DVD player analog video outputs, automotive infotainment rear-seat displays, video surveillance DVRs, and professional broadcast monitor test patterns. The encoder is also used in industrial video test equipment where a clean, standards-compliant analog video reference is required. When designing with this part, allocate separate analog and digital ground planes joined at a single star point beneath the exposed pad, place the analog supply decoupling capacitors within 5 mm of the AVDD pins, and avoid routing digital video data lines under the DAC output traces to minimize crosstalk into the reconstructed analog signal. This page synthesizes distributor pricing, datasheet pinouts, drop-in same-package alternatives, and practical analog PCB layout notes not collated in the manufacturer datasheet.
ADV7391WBCPZ-RL - 10-Bit HD Video Encoder, 32-LFCSP | Analog Devices
The Analog Devices ADV7391WBCPZ-RL is a low-power, chip-scale 10-bit SD/HD video encoder integrating three 10-bit video DACs in a 32-lead LFCSP (5x5 mm) package with exposed pad. It supports SD (NTSC/PAL/SECAM) and HD (720p/1080i/1080p) video standards from a single analog supply rail. The encoder provides simultaneous CVBS, S-Video, and component (YPbPr/RGB) analog outputs through three 10-bit DAC channels, each capable of driving standard 75-ohm video loads. A video encoder is an integrated circuit that converts digital video pixel data (typically ITU-R BT.656, BT.601, or BT.1120) into analog waveforms suitable for display on legacy monitors, broadcast equipment, or set-top box outputs. Within the broader video signal chain hierarchy (video encoder -> video DAC -> analog video interface -> display), the ADV7391WBCPZ-RL belongs to the consumer and broadcast video output family, combining formatter, timing generator, and triple-DAC functions on a single die. Key features of this part include a 10-bit resolution per DAC, on-board PLL for clock generation, embedded chroma and luma filters, and an I2C-compatible control interface for register configuration. It supports 8-bit ITU-R BT.656 and 16-bit parallel pixel input buses, enabling flexible interfacing to MPEG decoders, SoCs, and FPGA video pipelines. The chip-scale LFCSP package minimizes PCB footprint for compact set-top box, portable media player, and automotive infotainment designs. Technically, the device operates from a 1.8V digital supply and a 3.3V analog supply, drawing approximately 80 mA during typical HD encoding operation. Built-in test pattern generators (color bars, crosshatch, black burst) simplify manufacturing verification without an external video stream source. Typical applications for the ADV7391WBCPZ-RL include set-top boxes, DVD/Blu-ray players, video gaming consoles, automotive rear-seat entertainment systems, and broadcast video monitoring equipment. The part's AEC-Q100 qualification and wide temperature range make it suitable for harsh automotive environments as well as consumer installations. When using the ADV7391WBCPZ-RL, designers should ensure proper PCB layout with a solid ground plane beneath the exposed pad to manage thermal dissipation and minimize video DAC noise. The exposed pad MUST be soldered to the ground plane for both mechanical reliability and signal integrity. Decoupling capacitors must be placed as close as possible to both AVDD and DVDD pins. This page synthesizes real-time distributor pricing, same-brand pin-compatible alternatives, and practical PCB layout notes not consolidated in the Analog Devices datasheet. All data was verified against the manufacturer datasheet (Rev. K) and three distributor sources on 2026-10-20.
ADV7393WBCPZ-REEL - 10-Bit SD/HD Video Encoder | Analog Devices
The Analog Devices ADV7393WBCPZ-REEL is a low-power, 10-bit SD/HD video encoder offered in a 40-pin LFCSP-WQ (6x6 mm) package, with three integrated 10-bit video DACs supporting composite, S-Video (Y-C), and component (YPrPb) outputs. Fabricated on a single monolithic die, it accepts digital video inputs in numerous formats and provides hardware-flexible output standards including SD (NTSC/PAL) and HD (720p/1080i). The wide-range data interface and integrated scalar simplify downstream host MCU and FPGA connections in display pipelines. A video encoder (also called a video DAC or video digital-to-analog converter IC) is a semiconductor device that converts a digital video stream (parallel ITU-R BT.656, BT.1120, or similar) into an analog baseband waveform that legacy televisions, set-top boxes, automotive infotainment displays, and broadcast equipment can decode. The encoder sits downstream of a video decoder, scalar, or media processor and upstream of the physical analog connector or modulator, and belongs to the wider hierarchy: video encoder -> data converter IC -> mixed-signal semiconductor -> display pipeline IC. By consolidating the three DACs, sync insertion, and macrovision copy-protection on one die, the part replaces what historically required multiple discrete converters. Key differentiating features include three 2.7 V/3.3 V 10-bit DACs operating up to 80 MHz (sufficient for 720p/1080i HD timings), 1.8 V or 3.3 V digital I/O to ease interfacing with modern application processors, integrated on-chip voltage reference, single 27 MHz crystal or clock input, and a 2-wire I2C-compatible control interface. The 40-lead LFCSP-WQ package with an exposed thermal pad keeps PCB real-estate modest while supporting up to -40 to +105 degC operation, while advanced power management reduces shutdown current to microamp levels for portable video applications. Internally, the encoder uses a current-steering DAC architecture with proprietary dynamic element matching to maintain low spurious content and good differential linearity at HD data rates. A configurable input formatter accepts YCbCr 4:2:2 or 4:4:4 video and supports separate syncs, embedded syncs (SAV/EAV), and a 16/24-bit parallel host port. Host-side firmware configures output standard, pedestal, gamma, and color-bar test pattern through the I2C control port, removing the need for external glue logic. Typical applications include set-top boxes, Blu-ray and DVD players, automotive infotainment rear-seat displays, video capture and editing cards, medical imaging preview outputs, and digital signage. The combination of SD and HD support on one IC, plus the small 6x6 mm footprint and -40 to +105 degC operating range, makes the part well suited to multi-standard platforms where a single hardware design must serve global SKUs. When designing with this device, ensure the host processor supplies an ITU-R BT.656 or BT.1120 stream with proper EAV/SAV codes; the encoder auto-detects SD vs HD mode from the input line length, but the host must configure the output standard via I2C on power-up. The exposed thermal pad must be soldered to a continuous ground copper pour of at least 1 square inch to keep the die within safe junction temperature under sustained HD output operation.
EL1881CSZ-T7 - Video Sync Separator 8-SOIC | Renesas
The Renesas Electronics EL1881CSZ-T7 is a monolithic video sync separator IC manufactured using a high-performance analog CMOS process that extracts timing information from standard and non-standard composite video inputs. The device accepts input from NTSC, PAL, and SECAM video formats, supports supplies from 5V (typical), and delivers composite sync, vertical sync, burst/back porch timing, and odd/even field detection outputs from an 8-pin SOIC (0.154" / 3.90 mm) package with a tape-and-reel shipping format. What is a video sync separator? A video sync separator is a type of analog interface IC in the broader family of video processing ICs that slice the synchronization pulses from the composite video waveform, allowing downstream timing circuits to reconstruct line- and field-rate clocks. In the hierarchy video sync separator -> video processing IC -> interface IC -> integrated circuit, these devices sit between the analog video front end and the digital video processor, providing the timing reference that determines where each scan line begins and ends. Key features of the EL1881CSZ-T7 include a fixed 70 mV sync-tip slicing threshold, support for non-standard video with input amplitudes as low as 0.5 Vp-p, and outputs for composite sync, vertical sync, burst/back porch timing, and odd/even field identification. The fixed slicing level provides stable sync-edge detection even when the input signal amplitude varies, eliminating the need for external slicing adjustment. The IC operates from a single 5 V rail with lower supply current than the industry-standard LM1881, making it suitable for power-sensitive designs. The EL1881CSZ-T7 is built on a CMOS process that combines analog signal conditioning with the low power consumption typical of CMOS. Its coupling flexibility allows operation with both AC- and DC-coupled video sources, and it extracts timing from non-standard formats that would defeat traditional sync slicers. The device is specified for the commercial operating temperature range and is shipping in production today from authorized Renesas distributors. Typical applications include broadcast and consumer video equipment, video capture and editing systems, surveillance and security camera signal conditioning, industrial video inspection systems, and legacy analog TV and DVD player signal paths. The EL1881CSZ-T7 is also used in video format converters where the sync must be regenerated for downstream digitizers. When designing with the EL1881CSZ-T7, AC-couple the video source to the device input and place bypass capacitors close to the supply pin. Ensure that the input signal amplitude is at least 0.5 Vp-p to guarantee valid sync-tip detection. The sync outputs are TTL-compatible and can drive standard digital logic directly without level shifting. This page synthesizes distributor pricing from Renesas authorized channels, drop-in alternatives including the industry-standard LM1881, and practical design notes that complement - and extend - the manufacturer datasheet.
FT812Q-R - Advanced EVE Graphics Controller, 56-QFN, Bridgetek
The Bridgetek FT812Q-R is an Advanced Embedded Video Engine (EVE) graphics controller IC with SPI host interface, housed in a 56-pin QFN (8x8 mm) package with exposed thermal pad. It integrates a 24-bit RGB display controller, resistive touch controller, audio processor, and graphics engine on a single chip, targeting high-resolution HMI (human-machine interface) applications with screen sizes up to 800x600 and beyond. The part operates from a single 2.97V to 3.63V supply and supports 1.8V or 3.3V host SPI I/O via separate VDDIO. An Embedded Video Engine (EVE) is a category of HMI bridge IC that combines display, touch, and audio control into a single SPI/I2C-controlled device. EVE controllers sit in the hierarchy: display controller -> HMI bridge IC -> video interface -> integrated circuit -> semiconductor. They offload graphics rendering, widget management, and touch scanning from the host MCU, replacing discrete display driver ICs, touch controllers, and audio DACs with a unified graphics pipeline. Key features include a hardware-accelerated graphics engine with built-in widgets (buttons, sliders, gauges, clocks, dials), up to 51MHz SPI clock for fast image transfer, integrated resistive touch scanning controller with built-in ADC, I2S audio engine output for audio playback, and 8-bit or 16-bit 8080/6800 parallel plus 4-wire SPI/QSPI host interface options. The part supports up to 800x600 with display over in RGB mode and includes backlight PWM output for direct LCD backlight control. Architecturally, the FT812Q-R pairs an embedded graphics accelerator with dual-ported display memory (1MB internal SRAM), reducing host MCU MIPS load to 5-10% of equivalent software-only rendering. The device is pin-compatible with the FT810/FT811 family, simplifying upgrades for designs that need higher resolution or audio support. Typical applications include industrial HMI panels, smart home control displays, medical device touchscreens, point-of-sale (POS) terminals, and automotive infotainment entry-level displays. Designers choose the FT812Q-R over FPGA- or MCU-based solutions when they need to minimize host MCU MIPS load, BOM cost, and PCB area while adding polished graphics. Design tip: ensure SPI traces are length-matched and the exposed thermal pad is soldered to a sufficient copper pour (at least 25 sq mm) for thermal performance; insufficient ground cooling can trigger internal thermal foldback at high operating temperatures. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
MAX7456EUI+T - Monochrome OSD Generator with EEPROM, 28-TSSOP-EP | Analog Devices
The Analog Devices (formerly Maxim Integrated) MAX7456EUI+T is a single-channel monochrome on-screen display (OSD) generator integrated circuit that combines a 256-character font ROM, non-volatile character memory (NVRAM), video sync separator, video driver, and SPI-compatible serial interface in a single 28-pin TSSOP-EP package. Designed for NTSC and PAL video systems, the MAX7456EUI+T displays up to 256 user-programmable 12x18-pixel characters at row 1 (top of frame), row 14 (middle), or row 26 (bottom), and integrates a video output driver that delivers a 2 Vp-p composite signal directly into a 75 ohm terminated load. An OSD (on-screen display) generator is a specialized mixed-signal IC that overlays text, graphics, and icons onto a composite video stream in applications where a graphical overlay is required without a full graphics controller. The MAX7456EUI+T belongs to the video processing IC family within the broader signal-chain and display-driver semiconductor hierarchy. It serves markets requiring character-based overlays in security camera menus, drone telemetry, industrial HMI, and consumer VCR/DVD equipment, eliminating the need for external video drivers, sync separators, switches, and EEPROM storage. This integration lowers system BOM cost, PCB area, and design risk. Key differentiating features include on-chip 256-character NVRAM (no external EEPROM required), built-in video output buffer (saves an op-amp), integrated sync separator for composite video or separate sync input, SPI serial control interface (compatible with 3.3 V and 5 V microcontrollers), and 2 Vp-p output drive into 75 ohm. The device operates from a single 5 V analog supply with a separate 3.3 V digital supply, supports 256 user-programmable characters, and provides automatic NTSC/PAL detection with 9.6 kB/s maximum character upload rate. Architecturally, the MAX7456EUI+T combines an analog video path (sync separator, clamp, video DAC, output buffer) with a digital control section (character memory, font ROM, address registers, SPI slave). The on-chip NVRAM uses Maxim's Zener-based non-volatile memory technology, which the manufacturer notes has a limited write endurance (specified in the datasheet). Designers should treat the NVRAM as configuration storage, not as a high-cycle-count working buffer. Typical applications include closed-circuit television (CCTV) and IP camera menu overlays, FPV drone OSD for telemetry and flight data, industrial machine vision HMI, set-top box user interface overlays, consumer VCR/DVD on-screen menus, and avionics or marine instrumentation display overlays. The MAX7456EUI+T suits any video-based system that needs non-volatile, persistent on-screen information without a full graphics processor. When designing with this device, verify NVRAM write endurance against expected menu-update frequency, and provide adequate decoupling on both the analog 5 V (VDD) and digital 3.3 V (VDD_DIG) rails to suppress switching noise coupling into the analog video output. Designers should also confirm the upstream video source provides proper sync polarity, as the MAX7456EUI+T expects NTSC/PAL standard composite video or separate HSync/VSync inputs. This page synthesizes distributor pricing, lifecycle status, and cross-reference guidance for the MAX7456EUI+T, including identification of the third-party AT7456E clone marketed as a drop-in substitute on certain distributor channels, and engineering considerations for transitioning away from this obsolete part.
SI21662-B22-GMR - Dual DVB-S/S2 Satellite TV Demodulator | Skyworks
The Skyworks SI21662-B22-GMR is a dual-channel DVB-S, DVB-S2 and DSS satellite TV digital demodulator integrated into a single 68-pin QFN (8x8 mm) package. Each of the two independent demodulator cores supports QPSK, 8PSK, 16APSK and 32APSK modulation, with symbol rates up to 45 Msps for legacy DVB-S and up to 30 Msps for DVB-S2. The device is intended for satellite set-top box, PVR, and TV front-end designs that must tune two transponders simultaneously for picture-in-picture or dual-record functionality. Host communication is via a standard I2C serial interface (TBC specific address) operating from a single 3.3 V supply, and the part is delivered on 2500-piece tape and reel in the GMR (Pb-free matte-tin, RoHS compliant) finish. A satellite demodulator is a category of baseband signal-processing IC that converts the digitized IF output from a tuner into MPEG transport streams (or LVDS / parallel TS to an external host decoder). It belongs to the broader hypernym hierarchy: demodulator -> tuner/demodulator can -> receiver subsystem -> digital TV front-end -> consumer video SoC ecosystem. Modern DVB-S2 systems additionally apply LDPC forward-error-correction, so an Si2166x family device must pair with a low-noise PLL that meets the phase-noise mask demanded by 32APSK constellations. Key features include dual independent DVB-S/DVB-S2/DSS demodulation channels, 32APSK and 16APSK support for high-efficiency DVB-S2 transponders, integrated LDPC and BCH FEC engines, DiSEqC 1.x and 2.x interface support, and a flexible TS output interface with serial, parallel and LVDS options. An on-chip programmable clock recovery synthesizer removes the need for an external VCXO in most designs, reducing BOM cost. The 68-QFN (8x8 mm) exposed-pad package supports a thermal resistance (theta_JA) suitable for the typical 0.6 W power dissipation of the device under full dual-channel load. The SI21662-B22-GMR uses Skyworks' proprietary dual demodulator core architecture that shares the analog AGC loop and host interface between channels. Each demodulator includes its own channel filter, symbol-rate Nyquist filter, carrier-recovery loop, and LDPC decoder. The device is implemented in a standard CMOS process and supports both legacy DVB-S (QPSK) and the second-generation DVB-S2 standard with multi-level APSK constellations, giving receiver manufacturers a single silicon platform for legacy SD, HD, and UHD satellite transponder decoding. Typical applications include dual-tuner satellite set-top boxes, hybrid satellite/terrestrial DVRs, professional satellite receiver cards, and television sets with built-in DVB-S2 tuners. The dual-channel architecture is particularly suited to watch-and-record scenarios where one tuner is dedicated to a live channel while the second records a different transponder simultaneously. The integrated DiSEqC interface also makes the part a natural fit for multi-LNB dish installations such as motorised DiSEqC 1.2 / 2.x setups. When designing with the SI21662-B22-GMR, provide a clean 3.3 V regulated analog rail (LDO) and short, impedance-controlled IF traces from the tuner output, because the demodulator's symbol-timing recovery is sensitive to phase noise on both the IF and the reference clock. Use a 100 nF decoupling capacitor on every VDD pin and a single 10 uF bulk capacitor on the 3V3 supply pin. This page synthesizes distributor pricing, drop-in Si2166x family alternatives, pinout guidance, and design notes that go beyond what the manufacturer datasheet alone provides for the SI21662-B22-GMR.
TDA19989BET/C1,518 - HDMI 1.4 Transmitter 150MHz | NXP
The NXP Semiconductors TDA19989BET/C1,518 is a 150 MHz pixel-rate HDMI 1.4 transmitter IC with integrated HDCP 1.3 copy protection, CEC support, and an I2C control interface, housed in a 64-TFBGA (4.5 x 4.5 mm) ball grid array package. An HDMI transmitter IC is a digital video interface device that encodes parallel video pixel data into TMDS (Transition Minimized Differential Signaling) serial streams for transmission over HDMI or DVI links. Within the system hierarchy, it sits in the video signal chain between a graphics source such as a SoC, microcontroller, or video processor and the HDMI physical connector, converting ITU656/parallel RGB video input into a standards-compliant high-definition multimedia output. Key features of the TDA19989BET/C1,518 include support for up to 150 MHz pixel clock rates (enabling 1080p60 resolution), compliance with HDMI v1.3a and HDMI 1.4 specifications, HDCP 1.3 content protection for encrypted media streams, and compatibility with CEA-861B, DVI 1.0, and ITU656 video standards. The device provides three 8-bit video input paths and is fully controlled through a standard I2C serial interface, allowing a host processor to configure resolution, color depth, and HDCP sessions. Technically, the transmitter integrates TMDS clock and data serialization, audio embedding over HDMI, InfoFrame generation, and CEC (Consumer Electronics Control) messaging, reducing external component count in set-top box and AV receiver designs. The 64-TFBGA (4.5 x 4.5 mm) surface-mount package suits space-constrained consumer video boards while supporting the high-speed differential routing required for TMDS signals. Typical applications include set-top boxes, AV receivers, digital televisions, and HDMI-enabled embedded graphics boards. The 150 MHz pixel rate covers all standard 1080p video formats and their associated embedded audio streams. Design consideration: HDCP 1.3 operation requires careful I2C firmware handling and licensed HDCP keys; TMDS output pairs demand controlled-impedance PCB routing with matched lengths to maintain signal integrity at 150 MHz pixel rates. Note: this part is listed as Obsolete by supplier datasheet databases (Part Status: Obsolete); it remains procurable through surplus and broker channels. This page synthesizes distributor availability, specification data, family alternatives, and design guidance not found on any single distributor page.
TVP5150AM1IPBSR - Ultra-Low Power NTSC/PAL/SECAM Video Decoder | TI
The Texas Instruments TVP5150AM1IPBSR is an ultra-low-power NTSC/PAL/SECAM video decoder that converts analog composite or S-Video inputs to digital ITU-R BT.656 formatted output. It integrates a high-speed 9-bit ADC, supports two composite or one S-Video input, and is housed in a 32-pin TQFP (PBS) 5x5mm package. Operating from 1.65 V to 1.95 V analog and 1.65 V to 3.6 V digital supplies, the device consumes only 115 mW typical, making it ideal for portable and battery-powered imaging systems. What is a video decoder? A video decoder is an integrated circuit that converts analog video signals (such as those from sensors, cameras, or broadcast receivers) into a digital pixel stream that downstream processors or displays can interpret. Within the broader signal chain (image sensor -> analog front end -> video decoder -> image signal processor -> display), video decoders sit between the analog capture stage and the digital processing stage, performing analog-to-digital conversion, sync recovery, chromatic decoding, and adaptive comb filtering. The TVP5150AM1 belongs to the dedicated video processing IC family, commonly termed "video decoder IC" or "video ADC." Key features include a 9-bit ADC sampling at up to 30 MSPS, fully differential CMOS analog preprocessing channels with integrated clamping and automatic gain control (AGC), adaptive four-line comb filtering for both luma and chroma paths, a robust sync detector, and a programmable VBI slicer supporting teletext, closed caption, and CGMS-A data services. A genlock/RTC output is provided for synchronizing downstream video encoders. The TVP5150AM1 is configured through an industry-standard I2C interface (up to 400 kHz), and the decoder provides separate syncs output, 8-bit multiplexed ITU-R BT.656 output, and 16-bit YCbCr output formats. Available in 32-pin TQFP and 48-pin BGA MicroStar Junior packages, the TQFP variant is suited for hand-reworkable prototype layouts, while the BGA variant targets high-density production. Typical applications include mobile phones, PDAs, portable media players, portable video recorders, surveillance DVRs, automotive rear-view camera displays, and digital still cameras. AEC-Q100 qualification also enables use in automotive vision ECUs. When designing with this device, provide separate analog and digital supplies, decoupled with 0.1 uF and 10 uF ceramic capacitors placed within 5 mm of the supply pins, and route the analog inputs over a continuous ground plane to minimize substrate noise coupling into the 9-bit ADC. This page synthesizes cross-brand alternatives, ready-stock distributor tiers, and design notes beyond those in the manufacturer datasheet to accelerate part selection and downstream schematic capture.