ADF4112BCPZ vs ADF4113BCPZ Comparison
Detailed side-by-side comparison of ADF4112BCPZ by Analog Devices and ADF4113BCPZ by Analog Devices. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | ADF4112BCPZ | ADF4113BCPZ |
|---|---|---|
| Brand | Analog Devices | Analog Devices |
| Category | Clock & Timing | Clock & Timing |
| Lifecycle Status | Active | Active |
| Product Type | Integer-N RF PLL frequency synthesizer | Single integer-N RF PLL frequency synthesizer |
| Maximum Synthesized Frequency | 3 GHz | — |
| RF Bandwidth | 4 GHz | — |
| Input Frequency Range | 5 MHz to 3 GHz | — |
| Supply Voltage | 3.3 V | — |
| Input Logic | CMOS or TTL | — |
| Output Type | Clock | Clock |
| Architecture | Single integer-N PLL | — |
| Prescaler Ratios | 4/5 or 8/9 | — |
| A Counter | 6 bits | 6 bits |
| B Counter | 13 bits | 13 bits |
| Charge Pump | Programmable current | — |
| VP Connection | Separate connection for extended tuning voltage | — |
| Package | 20-lead LFCSP with exposed pad | 20-lead LFCSP with exposed pad |
| Number of Circuits | 1 | — |
| Mounting Type | Surface mount | Surface mount |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Phase Noise | [DATA_NEEDED: phase noise] | — |
| Locking Time | [DATA_NEEDED: locking time] | — |
| Output Buffer Current | [DATA_NEEDED: output buffer current] | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| REACH Status | [DATA_NEEDED: REACH status] | [DATA_NEEDED: REACH status] |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | [DATA_NEEDED: AEC-Q100 qualification] |
| Maximum RF Output Frequency | — | 4 GHz |
| Minimum RF Operating Frequency | — | 5 MHz |
| Maximum Reference Input Frequency | — | 165 MHz |
| PLL Architecture | — | Integer-N |
| Number of Synthesizers | — | 1 |
| Prescaler | — | Programmable dual-modulus P/P+1 |
| Input Logic Level | — | CMOS/TTL |
| Supply Voltage Range | — | [DATA_NEEDED: supply voltage range] |