ATF22V10C-7JU vs ATF22V10C-7JI Comparison
Detailed side-by-side comparison of ATF22V10C-7JU by Microchip Technology and ATF22V10C-7JI by Microchip Technology. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Microchip Technology
ATF22V10C-7JU - 10-Macrocell 7 ns PLD | Microchip | PLCC
ATF22V10C-7JU ✓ Active
Specification Comparison
| Parameter | ATF22V10C-7JU | ATF22V10C-7JI |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Category | Logic ICs | Logic ICs |
| Lifecycle Status | Active | Obsolete |
| Device Type | Electrically Erasable Programmable Logic Device (EEPLD) | — |
| Logic Family | ATF22V10C SPLD | — |
| Gate Count | 500 gates | — |
| Macrocells | 10 macrocells | — |
| Nominal Supply Voltage | 5 V | — |
| Minimum Operating Voltage | 4.5 V | — |
| Maximum Operating Voltage | 5.5 V | — |
| Speed Grade | 7 ns | — |
| Propagation Delay | 7.5 ns | 7.5 ns |
| Maximum Device Frequency | 166 MHz | — |
| Configuration Memory | Electrically Erasable Flash | — |
| Power-Down Mode | Optional pin-controlled power-down | — |
| Typical Power Dissipation | 10 uA | — |
| Package | 28-pin PLCC | 28-LCC (J-Lead), 11.51 mm x 11.51 mm |
| Package Dimensions | 11.51 mm x 11.51 mm | — |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| REACH Status | [DATA_NEEDED: REACH status] | [DATA_NEEDED: REACH status] |
| Product Type | — | EE PLD |
| Device Series | — | 22V10 |
| Number of Macrocells | — | 10 macrocells |
| Equivalent Gate Capacity | — | 500 gates |
| Input Voltage | — | 5 V |
| Programmable Technology | — | Electrically Erasable Flash memory |
| Architecture | — | CMOS |
| PLCC Package Code | — | QCCJ |
| Terminal Form | — | J Bend |
| Number of Terminals | — | 28 |
| Temperature Grade | — | Industrial |
| Power-Down Control | — | Optional pin-controlled power-down on PLCC pin 5 |
| Latch Feature | — | Holds inputs at previous logic states |
| AEC-Q100 Status | — | [DATA_NEEDED: AEC-Q100 qualification status] |