ATSAMA5D225C-D1M-CUR vs ATSAMA5D28B-CN Comparison
Detailed side-by-side comparison of ATSAMA5D225C-D1M-CUR by Microchip Technology and ATSAMA5D28B-CN by Microchip Technology. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Microchip Technology
ATSAMA5D225C-D1M-CUR - ARM Cortex-A5 MPU 500MHz 128Mbit DDR2 | Microchip
ATSAMA5D225C-D1M-CUR ✓ ActiveMicrochip Technology
ATSAMA5D28B-CN - Cortex-A5 500MHz MPU, 128MB DDR2 | Microchip
ATSAMA5D28B-CN ✓ ActiveSpecification Comparison
| Parameter | ATSAMA5D225C-D1M-CUR | ATSAMA5D28B-CN |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Category | Microcontrollers | Microcontrollers |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.80 | $17.95 |
| Family | SAMA5D2 Series | — |
| Core | ARM Cortex-A5 (32-bit, single-core) | — |
| Maximum CPU Clock | 500 MHz | 500 MHz |
| Integrated Memory | 128 Mbit DDR2 SDRAM (16-bit data bus) | — |
| Package | 196-ball TFBGA, 11x11 mm, 0.8 mm pitch | 289-ball LFBGA, 14 mm x 14 mm |
| Mounting Type | Surface Mount (BGA) | Surface Mount (BGA) |
| Operating Temperature Grade | Industrial (-40C to +85C) | — |
| Security | Arm TrustZone, tamper detection, secure boot, secure data storage | — |
| Cryptography | AES, SHA, TRNG hardware accelerators | — |
| Graphics | LCD TFT controller (up to 1024x768) | — |
| Touch Controller | Peripheral Touch Controller (PTC) | — |
| Audio | Embedded audio subsystem with sample-rate converters | — |
| Connectivity | 10/100 Ethernet MAC, USB HS Host/Device, CAN-FD, multiple SPI/I2C/UART | — |
| MSL Level | [DATA_NEEDED: MSL level] | 3 (168 hours) |
| RoHS Status | Compliant (BGA GREEN) | Compliant |
| Supply Voltage | [DATA_NEEDED: VDD core/IO supply range] | 3.3 V I/O, 1.2 V core (internal LDO) |
| Boot Media Supported | QSPI NOR, NAND, eMMC, SD card | — |
| Tape & Reel Packaging | Yes (per Mouser listing) | — |
| Core Architecture | — | Arm Cortex-A5 (Armv7-A) |
| FPU | — | VFPv4 (single/double precision) |
| L1 Instruction Cache | — | 32 Kbytes |
| L1 Data Cache | — | 32 Kbytes |
| L2 Cache | — | 128 Kbytes (configurable as SRAM) |
| MMU | — | Yes (full translation) |
| TrustZone | — | Yes (Arm TrustZone) |
| NEON Media Engine | — | Yes (SIMD) |
| Integrated DRAM | — | 128 Mbytes DDR2/DDR3L/LPDDR2/LPDDR3 controller |
| External Memory Bus | — | 16-bit ECC-capable |
| USB Controllers | — | 2x USB 2.0 High-Speed (Host/Device) |
| Ethernet | — | 10/100 MAC with IEEE 1588 + GMAC |
| CAN | — | 2x CAN-FD |
| SD/MMC | — | 3x SD/SDIO/MMC/e.MMC |
| UART / SPI / I2C | — | Multiple instances (peripheral multiplexing) |
| Crypto Accelerator | — | AES, SHA, TRNG, secure boot |
| Operating Temperature | — | -40 C to +85 C (industrial) |