ATSAMA5D23B-CU vs ATSAMA5D22B-CUR Comparison
Detailed side-by-side comparison of ATSAMA5D23B-CU by Microchip Technology and ATSAMA5D22B-CUR by Microchip Technology. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Microchip Technology
ATSAMA5D23B-CU - Cortex-A5 500MHz MPU, 196-TFBGA | Microchip
ATSAMA5D23B-CU β ActiveMicrochip Technology
ATSAMA5D22B-CUR - ARM Cortex-A5 500MHz MPU, 196-TFBGA | Microchip
ATSAMA5D22B-CUR β ActiveSpecification Comparison
| Parameter | ATSAMA5D23B-CU | ATSAMA5D22B-CUR |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Category | Microcontrollers | Microcontrollers |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $11.90 | $9.10 |
| Core Architecture | ARM Cortex-A5 (ARMv7-A) | ARM Cortex-A5 (32-bit, single-core) |
| Maximum Core Frequency | 500 MHz | β |
| Core Count | 1 | β |
| Internal SRAM | 128 KB | β |
| External Memory Interface | 16-bit DDR2/LPDDR/LPDDR2 | β |
| Package | 196-TFBGA (11x11 mm) | 196-TFBGA, 11x11 mm, 0.75 mm pitch |
| Ball Pitch | 0.8 mm | β |
| Supply Voltage | 1.2 V core | 0.9 V core / 1.8 V / 3.3 V I/O (typical) |
| Operating Temperature | -40C to +85C (industrial) | β |
| Backup Current | 5 uA typical | β |
| Graphics | Integrated LCD controller with 2D accelerator | β |
| Ethernet | Dual 10/100 EMAC | 10/100/1000 Mbps with IEEE 1588 |
| USB | USB 2.0 High-Speed Host + Device | USB 2.0 High-Speed Host and Device |
| CAN | Dual CAN-FD | 2x CAN-FD |
| ADC | 12-bit, 16-channel | β |
| RoHS Status | Compliant | Compliant |
| Mounting Type | Surface Mount (BGA) | Surface Mount |
| Maximum CPU Clock | β | 500 MHz |
| L1 Instruction Cache | β | 128 Kbyte |
| L1 Data Cache | β | 128 Kbyte |
| L2 Cache | β | 32 Kbyte |
| NEON Media Engine | β | Yes (NEON MPE) |
| Floating Point Unit | β | VFPv4-D32 (single and double precision) |
| External Memory Controller | β | 16-bit DDR2/LPDDR/LPDDR2/DDR3(L) |
| Display Controller | β | 24-bit LCD with overlays, 2D graphics accelerator |
| Video Decoder | β | H.264 / MPEG-4 / VP8 / JPEG hardware decode |
| Crypto Accelerator | β | AES, SHA, TRNG; ARM TrustZone secure boot |
| Operating Temperature (Industrial) | β | -40C to +85C |
| MSL Level | β | 3 (per JEDEC J-STD-020) |
| Deep-Sleep Current | β | <5 uA with backup self-refresh |