EP1810GC-35 vs EP1810JC35 Comparison

Detailed side-by-side comparison of EP1810GC-35 by Altera and EP1810JC35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP1810GC-35 EP1810JC35
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last Time Buy Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $177.12 $9.75
Device Type EPLD (Erasable Programmable Logic Device) —
Logic Family Altera Classic EPLD —
Technology CMOS, UV-erasable EPROM cells —
Package CPGA-68 (Ceramic Pin Grid Array, 68-pin) PLCC-68 (J-lead, ceramic)
Number of Pins 68 —
Propagation Delay (tpd max) 40 ns —
Maximum Inputs 64 —
Maximum Outputs 48 —
Macrocells 16 48
I/O Standard TTL-compatible —
Programming Method UV erasure + EPROM programming —
Operating Temperature [DATA_NEEDED: operating temperature range] 0 C to +70 C (Commercial)
Supply Voltage [DATA_NEEDED: VCC range] —
Mounting Type Through Hole —
RoHS Status Not applicable (legacy ceramic package) [DATA_NEEDED: RoHS compliance for EP1810JC35]
Lead-Free Status Not applicable —
Manufacturer (current source) Rochester Electronics (authorized Altera EPLD partner) —
Original Manufacturer Altera Corporation (now Intel FPGA) —
Family — Altera Classic EPLD
Product Type — UV-erasable / OTP Complex PLD (EPLD)
Logic Gates (typ.) — [DATA_NEEDED: logic gates count]
Maximum User I/O Pins — [DATA_NEEDED: user I/O count for PLCC-68]
Propagation Delay (tPD) — 35 ns
Maximum Clock Frequency — 40 MHz
Supply Voltage (VCC max) — 5.25 V
Supply Voltage (VCC min) — [DATA_NEEDED: VCC minimum]
Process Technology — CMOS EPROM cell
Package Code — QCCJ
Terminal Form — J-BEND
Number of Terminals — 68
Programming — UV-erase (windowed) or OTP
Development Tool — Altera MAX+plus II / A+plus

Datasheets & Resources

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