EP1810GM883 vs EP1810GM883B Comparison

Detailed side-by-side comparison of EP1810GM883 by Altera and EP1810GM883B by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP1810GM883 EP1810GM883B
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Stock Status In Stock In Stock
Unit Price (USD) $175.00 $125.40
Family Classic EPLD (EP1810 series) —
Device Type UV-Erasable Programmable Logic Device (EPLD) —
Macrocells 48 48
Dedicated Inputs 12 12
User I/O Pins 48 —
Total Terminals 68 —
Global Clocks 4 —
Supply Voltage (Vcc) 4.5 V to 5.5 V (nominal 5 V) —
Propagation Delay (tpd) 45 ns (max) —
Maximum Toggle Frequency (fmax) [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] —
Process Technology CMOS, UV-erasable —
Package 68-Pin Ceramic Pin Grid Array (PGA) —
Operating Temperature -55C to +125C (MIL-STD-883 Class B) -55 °C to +125 °C (Military, MIL-STD-883B)
Screening MIL-STD-883 Class B (suffix '883' denotes MIL processing) —
Mounting Type Through-Hole (PGA socket) Through-hole (PGA socket or PCB through-hole)
RoHS Status [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] —
Lead-Free [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] —
Device Family — EP1810 (Classic EPLD)
User Flip-Flops — Up to 64
Total Inputs — 60
I/O Pins — 48 (bidirectional, tri-state)
Propagation Delay (tPD) — 50 ns max
Supply Voltage (VCC) — 4.5 V to 5.5 V
Technology — CMOS, UV-erasable
Package Type — Ceramic Pin Grid Array (PGA), 84 pins
Package Designator — GM (ceramic PGA)
Processing Level — MIL-STD-883B (Class B)
Programming Method — UV-erasable / Altera programming hardware
Lead-Free / RoHS — [DATA_NEEDED: lead-free status]
Logic Family — TTL-compatible I/O

Datasheets & Resources

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