EP1810JC-45 vs EP1810JC35 Comparison
Detailed side-by-side comparison of EP1810JC-45 by Altera and EP1810JC35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1810JC-45 | EP1810JC35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $21.10 | $9.75 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | UV-erasable / OTP Complex PLD (EPLD) |
| Family | EP1810 (Classic EPLD Family) | Altera Classic EPLD |
| Macrocells | 48 | 48 |
| Equivalent Gates | 2100 gates | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| Total User I/O | 60 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Maximum Clock Frequency | 33.3 MHz | 40 MHz |
| Technology | CMOS, UV-erasable | — |
| Maximum Supply Voltage | 5.25 V | — |
| Package | PLCC-68 (QCCJ, J-Lead, windowed ceramic) | PLCC-68 (J-lead, ceramic) |
| Pin Count | 68 | — |
| Package Code | QCCJ | QCCJ |
| Temperature Grade | Commercial | — |
| Mounting Type | Surface Mount | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance not stated in verified data] | [DATA_NEEDED: RoHS compliance for EP1810JC35] |
| Logic Gates (typ.) | — | [DATA_NEEDED: logic gates count] |
| Maximum User I/O Pins | — | [DATA_NEEDED: user I/O count for PLCC-68] |
| Propagation Delay (tPD) | — | 35 ns |
| Supply Voltage (VCC max) | — | 5.25 V |
| Supply Voltage (VCC min) | — | [DATA_NEEDED: VCC minimum] |
| Process Technology | — | CMOS EPROM cell |
| Operating Temperature | — | 0 C to +70 C (Commercial) |
| Terminal Form | — | J-BEND |
| Number of Terminals | — | 68 |
| Programming | — | UV-erase (windowed) or OTP |
| Development Tool | — | Altera MAX+plus II / A+plus |