EP1810JI-45 vs EP1810JI-35 Comparison
Detailed side-by-side comparison of EP1810JI-45 by Altera and EP1810JI-35 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP1810JI-45 | EP1810JI-35 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $18.60 |
| Manufacturer | Altera (now Intel FPGA) | — |
| Series | Classic EPLD Family | — |
| Device Type | UV-Erasable / OTP Complex PLD | — |
| Macrocell Count | 48 | — |
| Maximum Operating Frequency | 33.3 MHz | — |
| Propagation Delay (tPD) | 50 ns | — |
| Configurable I/O Lines | 48 | — |
| Dedicated Inputs | 12 | 48 |
| Technology | CMOS EPROM | — |
| Package Code | QCCJ | — |
| Package Type | 68-pin JLCC (J-leaded ceramic chip carrier) | — |
| Terminal Form | J BEND | — |
| Package Shape | SQUARE | — |
| Number of Terminals | 68 | — |
| Temperature Grade | INDUSTRIAL | — |
| Operating Temperature | -40 °C to +85 °C | -40C to +85C (Industrial) |
| Supply Voltage | 5 V (TTL compatible) | 5 V (typical classic EPLD) |
| Programming Method | UV-erase (windowed) / OTP via JEDEC | — |
| Device Family | — | Classic EPLD |
| Macrocells | — | 48 |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Speed Grade | — | -35 |
| Package | — | 28-pin JLCC (J-leaded ceramic, windowed) |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| Mounting Type | — | Through-Hole (J-lead) |
| RoHS Status | — | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| MSL Level | — | [DATA_NEEDED: MSL rating] |
| Programming Interface | — | JEDEC fuse file via legacy programmer |