EP1C20F324C8 vs EP1C20F324C6 Comparison

Detailed side-by-side comparison of EP1C20F324C8 by Altera and EP1C20F324C6 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP1C20F324C8 EP1C20F324C6
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active NRND
Stock Status In Stock In Stock
Unit Price (USD) $32.00 $105.00
Part Number EP1C20F324C8 —
Product Family Cyclone I —
Number of Logic Elements 20,060 —
Number of LABs / CLBs 2,006 —
Total RAM Bits 294,912 —
Number of User I/Os 233 —
Package / Case 324-FBGA —
Total Pins / Balls 324 —
Core Supply Voltage 1.5 V —
Process Technology 130 nm 130 nm CMOS
Maximum Clock Frequency 275.03 MHz —
Speed Grade 8 6
Temperature Grade C (commercial) Commercial (0 °C to +85 °C)
Operating Temperature Range 0°C to 85°C (per C suffix) —
Mounting Type Surface Mount —
Transceivers None (hard transceivers not present on Cyclone I) —
Configuration Memory External EPCS serial configuration device recommended —
I/O Standards Supported [DATA_NEEDED: I/O standards supported] —
RoHS Status [DATA_NEEDED: RoHS status of non-N suffix version] —
REACH Status [DATA_NEEDED: REACH status] —
AEC-Q100 Not applicable (FPGA not AEC-Q100 listed) —
Family — Cyclone
Logic Elements (LE) — 20,060
Embedded RAM Bits — 294,912 bits (64 M4K blocks × 4,608 bits)
User I/O Count — 233
Core Voltage (VCCINT) — 1.5 V
I/O Voltage Standards — LVCMOS / LVTTL (3.3 V, 2.5 V, 1.8 V, 1.5 V), LVDS
PLLs — 4
Maximum Internal Frequency — 405.2 MHz
LVDS Data Rate (per pair) — Up to 640 Mbps
Memory Interfaces — DDR SDRAM, QDR SRAM, SDR SDRAM
Package — 324-ball FBGA (FineLine BGA)
Configuration Modes — Active Serial (AS), Passive Serial (PS), JTAG

Datasheets & Resources

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