EP1S80F1020C6 vs EP1S80F1020C7 Comparison

Detailed side-by-side comparison of EP1S80F1020C6 by Intel and EP1S80F1020C7 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP1S80F1020C6 EP1S80F1020C7
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $1,180.00 $195.00
Series Stratix Stratix
Logic Elements 79,040 79,040
Total RAM Bits 7,427,520 —
Number of Logic Blocks / LABs 9,191 —
Number of I/O Pins (max) 773 user I/O —
Number of Pins / Balls 1020 —
Package Type FC-FBGA (flip-chip fine-pitch BGA), 33 x 33 mm, 1.0 mm pitch FBGA-1020 (33 x 33 mm, 1 mm pitch)
Process Technology 130 nm CMOS 1.5 V, 0.13 um CMOS
Core Supply Voltage (VCCINT) 1.5 V nominal (1.425 V to 1.575 V) 1.425 V to 1.575 V
Speed Grade C6 —
Operating Temperature (Commercial) 0 C to +85 C —
Mounting Type Surface Mount Surface Mount (BGA)
Maximum Internal Clock Frequency 450.05 MHz —
Family Description FPGA - Field Programmable Gate Array —
Embedded Memory TriMatrix (three block sizes, true/simple dual-port) —
Configuration Interface JTAG (IEEE 1149.1) + serial/parallel configuration device —
Design Tool Quartus II (legacy, Stratix family) —
RoHS Status [DATA_NEEDED: rohs status] Compliant (lead-free FBGA)
Moisture Sensitivity Level (MSL) [DATA_NEEDED: MSL rating] —
System Gates (typical) — 7,427,520
Logic Array Blocks (LABs) — 7,904
User I/O Pins — 773
Total Package Pins — 1020 (ball)
Operating Temperature — 0 C to 85 C (Commercial)
Logic Family — CMOS, SRAM-based configuration
Configuration Modes — Passive Serial (PS), Fast Passive Parallel (FPP), JTAG
PLLs — 12 (per datasheet family)
Memory — TriMatrix embedded SRAM blocks
DSP Blocks — Dedicated hardware multipliers/accumulators

Datasheets & Resources

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