EP20K100ETC144-1N vs EP20K100ETC144-2N Comparison
Detailed side-by-side comparison of EP20K100ETC144-1N by Altera and EP20K100ETC144-2N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K100ETC144-1N
EP20K100ETC144-1N - APEX-20KE FPGA 100K Gates 144-LQFP | Altera
EP20K100ETC144-1N ObsoleteAltera
EP20K100ETC144-2N
EP20K100ETC144-2N - APEX-20KE FPGA, 100K Gates, 92 I/O | Altera
EP20K100ETC144-2N NrndSpecification Comparison
| Parameter | EP20K100ETC144-1N | EP20K100ETC144-2N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $55.80 | $22.00 |
| Family | APEX-20KE | APEX-20KE |
| Logic Elements | 53248 | β |
| Logic Cells | 4160 | β |
| System Gates | 100000 | β |
| User I/Os | 92 | β |
| Package | 144-LQFP (TQFP) | 144-LQFP (TQFP, 20x20 mm, 0.5 mm pitch) |
| Process Technology | 0.22 Β΅m CMOS | 0.22 Β΅m all-layer copper-metal |
| Core Voltage | 1.8 V | β |
| Operating Temperature | 0 Β°C to +85 Β°C | β |
| Embedded Array Blocks (EABs) | Yes (32-bit x 2K RAM/ROM/FIFO) | β |
| Configuration Interface | JTAG (IEEE 1149.1) / IEEE 1532 ISC | β |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Unknown [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Programming Software | MAX+PLUS II / Quartus II (legacy) | β |
| Device Series | APEX 20K 416 Macro 92 IOs | β |
| Device Type | β | FPGA (Field Programmable Gate Array) |
| Number of Logic Elements/Cells | β | 4160 |
| Number of LABs/CLBs | β | 416 |
| Total RAM Bits | β | 53248 |
| Number of Gates | β | 263000 (typical) |
| Number of User I/Os | β | 92 |
| Operating Supply Voltage (Core) | β | 1.71 V to 1.89 V (1.8 V nominal) |
| Maximum Operating Frequency | β | 250 MHz |
| Propagation Delay | β | 1.6 ns |
| Operating Temperature Range | β | 0 C to 85 C (TJ) |
| ESBs (Embedded System Blocks) | β | 4 |
| Programming Interface | β | JTAG (IEEE 1149.1) / FastON |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |