EP20K100QC208-1 vs EP20K100EQC208-3N Comparison

Detailed side-by-side comparison of EP20K100QC208-1 by Altera and EP20K100EQC208-3N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EP20K100EQC208-3N EP20K100EQC208-3N FPGA - 1.8V APEX-20KE | Altera

EP20K100EQC208-3N FPGA - 1.8V APEX-20KE | Altera

EP20K100EQC208-3N Obsolete

Specification Comparison

Parameter EP20K100QC208-1 EP20K100EQC208-3N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Family APEX 20K —
Device Type FPGA (Field Programmable Gate Array) —
Equivalent Logic Gates 100,000 —
Typical Gates 26,624 100000
Logic Elements / Cells 4,160 —
Embedded RAM 53,248 bits —
Maximum Operating Frequency 250 MHz —
Propagation Delay (tPD) 1.6 ns —
Speed Grade -1 -3
Supply Voltage (Core) 2.5 V —
Process Technology 0.22 µm CMOS [DATA_NEEDED: Process technology]
Number of PLLs 4 —
Package PQFP-208 (Plastic Quad Flat Pack) —
Pin Count 208 —
Mounting Type Surface Mount Surface Mount
Operating Temperature 0 °C to +85 °C (commercial) —
User I/Os (max) [DATA_NEEDED: exact user-IO count for PQFP-208] —
Configuration SRAM-based, volatile —
RoHS Status unknown —
Product Family — APEX-20KE
FPGA Type — Field Programmable Gate Array
Number of Logic Elements — 4160
System Gates — 263000
Total RAM Bits — 53248
Number of User I/O — 151
Core Supply Voltage — 1.8 V
Maximum Clock Frequency — 250 MHz
Package Type — 208-BFQFP (PQFP-208)
Number of Pins — 208
Operating Temperature Range — 0 °C to +85 °C
Propagation Delay — 2.2 ns
I/O Standards Supported — [DATA_NEEDED: Supported I/O standards]
Package Body Dimensions — [DATA_NEEDED: Package body dimensions]
Terminal Pitch — [DATA_NEEDED: Terminal pitch]
MSL Level — [DATA_NEEDED: MSL level]

Datasheets & Resources

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