EP20K1500CF33C8ES vs EP20K1000CF33I8N Comparison
Detailed side-by-side comparison of EP20K1500CF33C8ES by Intel and EP20K1000CF33I8N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K1500CF33C8ES | EP20K1000CF33I8N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last Time Buy | Obsolete |
| Series | APEX 20K (APEX 20KE family) | — |
| Manufacturer | Intel (formerly Altera) | — |
| System Gates | 1,500,000 | 1,000,000 (approx.) |
| Maximum Gates (Equivalent) | 2,392,000 | — |
| Logic Elements | 51,840 | 38,400 cells |
| Embedded System Block (ESB) Bits | 442,368 | — |
| CAM Bits | 216 Kbit | — |
| Number of PLLs | 4 | — |
| Number of Clocks | 8 clock pins | — |
| Maximum User I/O | 808 (1020-FBGA) | — |
| Package | 1020-FBGA (FCBGA), 33x33 mm | — |
| Mounting Type | Surface Mount | Surface Mount |
| Speed Grade | -1 (C8) | I8 |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | -40 °C to +85 °C (industrial) |
| Voltage - Supply (Core) | 1.8 V nominal (multiVolt I/O supports 1.8/2.5/3.3/5.0 V) | — |
| I/O Standard Support | LVTTL, LVCMOS, PCI, SSTL, HSTL, LVDS (multiVolt) | — |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| Programming Interface | ByteBlaster / MasterBlaster / Altera USB-Blaster | — |
| Sample Tier | ES (engineering sample) | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance for ES variant] | [DATA_NEEDED: rohs status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | APEX 20KC |
| Maximum Internal Clock Frequency | — | 301.21 MHz |
| Propagation Delay | — | 1.79 ns |
| Number of Logic Elements / Cells | — | 38,400 |
| Process Technology | — | 0.15 µm CMOS |
| Core Supply Voltage | — | 1.8 V nominal (1.71 V to 1.89 V) |
| Number of I/O Pins | — | 700 user I/O |
| Number of Pins | — | 1020 |
| Package Type | — | FC-FBGA-1020 (Flip-Chip Fine-pitch BGA) |
| Embedded Memory | — | Dual-port RAM via ESB blocks |
| PLL Count | — | 4 |
| Configuration Interface | — | IEEE 1149.1 JTAG, EPC serial/parallel |