EP20K400CF672C-8 vs EP20K400CF672C7GA Comparison
Detailed side-by-side comparison of EP20K400CF672C-8 by Altera and EP20K400CF672C7GA by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400CF672C-8 | EP20K400CF672C7GA |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | APEX 20K | — |
| Logic Elements | 16,640 | 212992 |
| Typical Gates | 400,000 | — |
| Macros | 1,664 | — |
| Maximum User I/O | 488 | — |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | — |
| Package Type | PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) | — |
| Core Voltage (VCCINT) | 1.8 V nominal (1.71 V to 1.89 V) | — |
| I/O Voltage (VCCIO) | [DATA_NEEDED: VCCIO options] | — |
| Pin-to-Pin Delay (tPD) | 1.78 ns (speed grade -8) | — |
| Speed Grade | -8 | C7 (7 ns pin-to-pin) |
| Temperature Grade (C) | Commercial, 0 °C to 85 °C | — |
| Process Technology | 0.15 µm all-layer copper CMOS | 0.18 um CMOS |
| Embedded Memory Type | ESB (RAM / ROM / CAM) | — |
| Configuration Interface | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| Mounting Type | Surface Mount (BGA) | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| MSL Level | [DATA_NEEDED: MSL level] | [DATA_NEEDED: moisture sensitivity level] |
| Series | — | APEX-20KC |
| Number of LABs/CLBs | — | 488 |
| Total RAM Bits | — | 16640 |
| Number of I/O | — | [DATA_NEEDED: max user I/O count] |
| Number of Gates | — | 400000 |
| Voltage - Supply | — | 2.5 V core |
| Package / Case | — | 672-BBGA (FineLine BGA) |
| Operating Temperature | — | 0C to +85C |
| Programming Method | — | In-System Programmable (ISP) via JTAG |
| Lead Free | — | [DATA_NEEDED: lead-free status] |