EP20K400CF672I8 vs EP20K400CF672I7 Comparison
Detailed side-by-side comparison of EP20K400CF672I8 by Intel and EP20K400CF672I7 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400CF672I8 | EP20K400CF672I7 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $190.50 |
| Family | APEX 20KC | APEX 20KC |
| Series | EP20K400 | β |
| Manufacturer | Intel (formerly Altera) | β |
| Device Type | FPGA - Field Programmable Gate Array | β |
| Logic Elements / Cells | 16,640 | β |
| System Gates | 400,000 | β |
| Embedded Memory (RAM bits) | 212,992 | β |
| Number of Logic Macros | 1664 | β |
| User I/O Pins | 488 | β |
| Supply Voltage - Core | 1.8 V | β |
| I/O Voltage (MultiVolt) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | β |
| Maximum Internal Frequency | 301.21 MHz | β |
| Process Technology | 0.15 Β΅m CMOS | 0.15 um CMOS |
| Speed Grade | I8 | I7 |
| Package Type | 672-pin FC-FBGA (FineLine BGA) | β |
| Operating Temperature (Industrial) | -40 Β°C to +100 Β°C | β |
| Mounting Type | Surface Mount (BGA) | β |
| Configuration Method | Passive Serial / Active Serial / JTAG (IEEE 1149.1) | β |
| PLLs | 4 | β |
| MSL Level | [DATA_NEEDED: MSL moisture sensitivity level] | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | β |
| Logic Elements | β | 16,640 |
| Maximum System Gates | β | 400,000 |
| Embedded Memory (ESB) | β | 212,992 bits |
| Maximum User I/O Pins | β | [DATA_NEEDED: pin count for CF672 package] |
| Core Supply Voltage | β | 1.8 V |
| I/O Supply Voltage | β | 1.8 V / 3.3 V |
| PLL Count | β | 4 |
| Operating Temperature | β | -40 C to +85 C (industrial) |
| Package | β | 672-ball FC-FBGA (Fine-pitch Chip-Scale BGA) |
| Terminal Finish | β | Tin/Lead (Sn/Pb) |
| JESD-609 Code | β | e0 |
| Moisture Sensitivity Level (MSL) | β | 3 |
| Configuration Mode | β | PS / AS / JTAG (IEEE 1149.1) |