EP20K400CF672I9 vs EP20K400CF672C9N Comparison
Detailed side-by-side comparison of EP20K400CF672I9 by Intel and EP20K400CF672C9N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400CF672I9 | EP20K400CF672C9N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements | 16,640 cells | 16,640 |
| System Gates | 400,000 | 400,000 |
| Maximum Operating Frequency | 250 MHz | 250 MHz |
| Embedded RAM | 212,992 bits | — |
| Embedded System Blocks (ESBs) | 104 | — |
| Maximum User I/O Pins | [DATA_NEEDED: max user I/O count] | — |
| Process Technology | 0.15 µm CMOS | 0.18 µm all-layer copper CMOS |
| Core Voltage | 1.8 V | 1.8 V |
| I/O Voltage | 1.8 V / 3.3 V (MultiVolt) | — |
| Package | 672-ball FC-FBGA (FineLine BGA) | 672-ball FC-FBGA |
| Package Pitch | 1.0 mm | — |
| Operating Temperature | -40°C to +85°C (Industrial) | 0 °C to 85 °C (commercial) |
| Speed Grade | I9 (Industrial) | — |
| Moisture Sensitivity Level (MSL) | 3 | — |
| Terminal Finish | e0 (Tin-Lead, per JESD-609) | — |
| RoHS Status | Non-compliant (e0 terminal finish indicates SnPb) | Compliant |
| Series | — | EP20K400 |
| Propagation Delay | — | 2.5 ns |
| User I/O Pins | — | 502 |
| Total I/O Lines | — | 480 |
| Dedicated Inputs | — | 4 |
| Embedded Memory | — | 212,992 bits |