EP20K400CFC672-9 vs EP20K400FC672-3 Comparison
Detailed side-by-side comparison of EP20K400CFC672-9 by Altera and EP20K400FC672-3 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400CFC672-9 | EP20K400FC672-3 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | APEX-20KC | APEX 20K |
| Logic Elements / Macrocells | 1664 | — |
| Typical Gate Count | 400,000 gates | 400,000 system gates |
| Embedded Memory (ESB) | 212,992 bits | — |
| User I/O Count | 488 | — |
| PLLs | 4 | — |
| Core Supply Voltage | 1.71 V to 1.89 V | 2.5 V |
| I/O Supply Voltage | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Operating Temperature (TJ) | 0 °C to 85 °C | — |
| Speed Grade | -9 (commercial, slowest bin) | -3 (commercial fastest) |
| Package | 672-ball FineLine BGA (FCBGA) | 672-pin FC-FBGA |
| Package Body Size | 27 mm × 27 mm | — |
| Mounting Type | Surface Mount (BGA) | Surface Mount |
| Configuration Method | EPC serial device or JTAG | — |
| Process Node | [DATA_NEEDED: process node] | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Device Logic Elements | — | 16,640 cells |
| Maximum User I/Os | — | 502 |
| Propagation Delay | — | 2.5 ns |
| Internal Performance | — | 167 MHz |
| Process Technology | — | 0.22 µm CMOS |
| Logic Family | — | CMOS, SRAM-based |
| Package Code | — | BGA |
| Number of Terminals | — | 672 |
| Terminal Form | — | Ball (BGA) |
| Operating Temperature | — | 0 °C to 85 °C |
| Architecture | — | MultiCore (LUT + Embedded System Blocks) |
| Programming Method | — | SRAM, JTAG (ByteBlaster) |
| Lifecycle Status | — | Obsolete / Legacy |