EP20K400GC655-1V vs EP20K400GC655-2V Comparison
Detailed side-by-side comparison of EP20K400GC655-1V by Altera and EP20K400GC655-2V by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K400GC655-2V - 400K Gate APEX-20KC FPGA 655-CPGA | Altera
EP20K400GC655-2V ⚠ Last Time BuySpecification Comparison
| Parameter | EP20K400GC655-1V | EP20K400GC655-2V |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last Time Buy |
| Family | APEX 20KE | APEX 20KC (1.8 V, LVDS) |
| Logic Elements | 16,640 | 16,640 |
| Typical Gate Count | 400,000 gates | — |
| Embedded Memory | 212,992 bits | — |
| Maximum User I/O | 496 | — |
| Dedicated Inputs | 6 | — |
| Package | CBGA-655 (Ceramic Ball Grid Array) | 655-CPGA (62.48 x 62.48 mm) |
| Total Terminals | 655 | — |
| Supply Voltage (Core) | 2.375 V to 2.625 V (nominal 2.5 V) | — |
| Propagation Delay | 2.5 ns | 3.000 ns |
| Maximum Internal Frequency | 250 MHz (-1V speed grade) | — |
| Process Technology | 0.22 µm CMOS | CMOS, 0.18 um |
| LVDS Support | Yes | Yes |
| Moisture Sensitivity Level | MSL 1 | — |
| Peak Reflow Temperature | 220 °C | — |
| Qualification | Not Qualified | — |
| Programming Interface | IEEE 1532 / JTAG | — |
| Series | — | APEX-20KC |
| Total RAM Bits | — | 212,992 |
| System Gates | — | ~400,000 (typical marketing figure) |
| Number of I/O | — | [DATA_NEEDED: I/O count] |
| Core Voltage (VCCINT) | — | 2.375 V to 2.625 V (nominal 2.5 V) |
| Package Type | — | Ceramic Pin Grid Array, through-hole |
| Mounting Type | — | Through-hole (CPGA) |
| Speed Grade | — | -2 |
| Operating Temperature | — | [DATA_NEEDED: temperature grade] |
| RoHS Status | — | unknown |
| Lead-Free | — | unknown |
| Architecture | — | MultiCore (LUT + product-term + embedded memory) |