EP20K400GC655-1X vs EP20K400GC655-3X Comparison

Detailed side-by-side comparison of EP20K400GC655-1X by Altera and EP20K400GC655-3X by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EP20K400GC655-1X EP20K400GC655-1X - 400K-Gate APEX 20K FPGA | Altera

EP20K400GC655-1X - 400K-Gate APEX 20K FPGA | Altera

EP20K400GC655-1X Obsolete

Specification Comparison

Parameter EP20K400GC655-1X EP20K400GC655-3X
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $193.04 $65.00
Product Family Altera APEX 20K β€”
Device Type Field Programmable Gate Array (FPGA) β€”
Technology CMOS β€”
Gate Count 400K gates β€”
Logic Elements 16640 cells β€”
Maximum System Frequency 250 MHz β€”
Propagation Delay 2.5 ns β€”
Core Supply Voltage 2.5 V β€”
I/O Supply Voltage 2.5 V / 3.3 V β€”
Number of User I/O 496 β€”
Number of Dedicated Inputs 6 β€”
Number of Terminals 655 β€”
Package Type CPGA-655 (Ceramic Pin Grid Array) β€”
Package Body Material Ceramic β€”
Process Technology 0.22 um 0.22 Β΅m CMOS
Operating Temperature Range [DATA_NEEDED: operating temperature range] β€”
Embedded RAM Bits [DATA_NEEDED: embedded RAM bits] β€”
RoHS Status unknown [DATA_NEEDED: RoHS status - ceramic CPGA historically non-RoHS]
Series β€” APEX-20KC
Family β€” APEX 20K (MultiCore architecture, LUT + product-term + embedded memory)
Manufacturer β€” Altera (now Intel FPGA)
Logic Elements / Cells β€” 16,640
System Gates β€” 400,000
Total RAM Bits β€” 212,992 bits
Maximum Internal Frequency β€” 167 MHz (speed grade -3)
Core Supply Voltage (VCCINT) β€” 1.71 V to 1.89 V
I/O Supply Voltage (VCCIO) β€” 2.5 V (LVDS support per APEX 20KE datasheet)
Package / Case β€” 655-BCPGA (CPGA655, 62.48 x 62.48 mm)
Mounting Type β€” Through-Hole (CPGA, ceramic)
Operating Temperature β€” [DATA_NEEDED: operating temperature range]
Speed Grade β€” -3 (fastest)
Suffix Code β€” -X (extended / ceramic CPGA variant)
I/O Count β€” [DATA_NEEDED: max user I/O]
JTAG / Boundary Scan β€” IEEE 1149.1 (per APEX 20K family)

Datasheets & Resources

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