EP20K400GC655-1X vs EP20K400GC655-3X Comparison
Detailed side-by-side comparison of EP20K400GC655-1X by Altera and EP20K400GC655-3X by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400GC655-1X | EP20K400GC655-3X |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Product Family | Altera APEX 20K | — |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Technology | CMOS | — |
| Gate Count | 400K gates | — |
| Logic Elements | 16640 cells | — |
| Maximum System Frequency | 250 MHz | — |
| Propagation Delay | 2.5 ns | — |
| Core Supply Voltage | 2.5 V | — |
| I/O Supply Voltage | 2.5 V / 3.3 V | — |
| Number of User I/O | 496 | — |
| Number of Dedicated Inputs | 6 | — |
| Number of Terminals | 655 | — |
| Package Type | CPGA-655 (Ceramic Pin Grid Array) | — |
| Package Body Material | Ceramic | — |
| Process Technology | 0.22 um | 0.22 µm CMOS |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | — |
| Embedded RAM Bits | [DATA_NEEDED: embedded RAM bits] | — |
| RoHS Status | unknown | [DATA_NEEDED: RoHS status - ceramic CPGA historically non-RoHS] |
| Series | — | APEX-20KC |
| Family | — | APEX 20K (MultiCore architecture, LUT + product-term + embedded memory) |
| Manufacturer | — | Altera (now Intel FPGA) |
| Logic Elements / Cells | — | 16,640 |
| System Gates | — | 400,000 |
| Total RAM Bits | — | 212,992 bits |
| Maximum Internal Frequency | — | 167 MHz (speed grade -3) |
| Core Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V (LVDS support per APEX 20KE datasheet) |
| Package / Case | — | 655-BCPGA (CPGA655, 62.48 x 62.48 mm) |
| Mounting Type | — | Through-Hole (CPGA, ceramic) |
| Operating Temperature | — | [DATA_NEEDED: operating temperature range] |
| Speed Grade | — | -3 (fastest) |
| Suffix Code | — | -X (extended / ceramic CPGA variant) |
| I/O Count | — | [DATA_NEEDED: max user I/O] |
| JTAG / Boundary Scan | — | IEEE 1149.1 (per APEX 20K family) |