EP20K400GC655-3V vs EP20K400GI655-3 Comparison
Detailed side-by-side comparison of EP20K400GC655-3V by Intel and EP20K400GI655-3 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400GC655-3V | EP20K400GI655-3 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Series | APEX-20KC | — |
| Family | APEX 20KC (Apex 20KE Device Family, 1.8 V, LVDS) | APEX 20KE |
| Manufacturer | Altera (now Intel) | — |
| Core Supply Voltage | 1.71 V to 1.89 V (1.8 V nominal) | 2.5 V |
| Logic Elements | 16640 | — |
| Total RAM Bits | 212992 | — |
| Typical Gate Count | 400000 | — |
| Number of User I/O | 496 | — |
| Maximum Clock Frequency | 714.2 MHz | — |
| Propagation Delay | 3.6 ns | — |
| Speed Grade | -3V (commercial temperature, Vcc 1.8 V) | -3 (slowest of the EP20K400 family) |
| Package | 655-BCPGA (62.48 mm x 62.48 mm) | 655-Pin PGA (Plastic/CPGA, square) |
| Package Equivalence Code | SPGA655, 47x47 | — |
| Mounting Type | Through Hole (CPGA) | Through-Hole (Socket) |
| Peak Reflow Temperature | 220 C | — |
| Process Technology | CMOS | CMOS, 2.5V core |
| Configuration | SRAM-based (requires EPC configuration device) | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance flag - BCPGA package often non-RoHS] | [DATA_NEEDED: RoHS status] |
| Operating Temperature | [DATA_NEEDED: commercial / industrial / military grade] | 0°C to 70°C (Industrial I grade) |
| Logic Elements / Cells | — | 16,640 |
| System Gates | — | 400,000 (maximum) |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 4 |
| Number of Terminals | — | 655 |
| JESD-30 Code | — | S-CPGA-P655 |
| Package Shape | — | Square |
| Form of Terminal | — | PIN/PEG (through-hole) |
| I/O Supply Voltage | — | 2.5 V or 3.3 V (MultiVolt I/O) |
| Configuration Modes | — | Passive Serial, Passive Parallel Asynchronous, JTAG |
| Embedded Memory | — | Dual-port RAM via Embedded System Blocks (ESBs) |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |