EP20K400GI655-3 vs EP20K400GC655-2 Comparison
Detailed side-by-side comparison of EP20K400GI655-3 by Altera and EP20K400GC655-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400GI655-3 | EP20K400GC655-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | APEX 20KE | APEX 20K |
| Logic Elements / Cells | 16,640 | — |
| System Gates | 400,000 (maximum) | 400,000 |
| Maximum User I/O | 502 | — |
| Dedicated Inputs | 4 | — |
| Number of Terminals | 655 | — |
| Package | 655-Pin PGA (Plastic/CPGA, square) | — |
| JESD-30 Code | S-CPGA-P655 | — |
| Package Shape | Square | — |
| Form of Terminal | PIN/PEG (through-hole) | — |
| Mounting Type | Through-Hole (Socket) | Through-Hole (CPGA) |
| Process Technology | CMOS, 2.5V core | 0.22 µm CMOS |
| Core Supply Voltage | 2.5 V | 2.5 V |
| I/O Supply Voltage | 2.5 V or 3.3 V (MultiVolt I/O) | 1.71 V to 1.89 V (MultiVolt) |
| Operating Temperature | 0°C to 70°C (Industrial I grade) | [DATA_NEEDED: operating temperature range] |
| Speed Grade | -3 (slowest of the EP20K400 family) | -2 |
| Configuration Modes | Passive Serial, Passive Parallel Asynchronous, JTAG | — |
| Embedded Memory | Dual-port RAM via Embedded System Blocks (ESBs) | — |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Series | — | APEX-20KC |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Logic Cells / Elements | — | 16,640 |
| Total RAM Bits | — | 212,992 |
| Maximum Internal Frequency | — | 200 MHz |
| LVDS Support | — | Yes |
| PLLs | — | 4 |
| Pin Count | — | 655 |
| Package Type | — | 655-BCPGA (CPGA-655) |
| Package Dimensions | — | 62.48 x 62.48 mm |