EP20K600CEF672C7 vs EP20K600CF672-3 Comparison

Detailed side-by-side comparison of EP20K600CEF672C7 by Intel and EP20K600CF672-3 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K600CEF672C7 EP20K600CF672-3
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Manufacturer Intel (formerly Altera) —
Series APEX 20KC —
Family APEX 20KC (Enhanced Configuration) APEX 20KC
Device Type FPGA / Loadable PLD —
Logic Elements / Cells 24,320 —
Gate Count (typical) 600,000 gates —
Maximum Operating Frequency 375.94 MHz —
Propagation Delay 1.48 ns (typ) —
User I/Os 488 —
Core Supply Voltage 1.8 V —
Process Technology 0.15 µm CMOS, all-layer copper 0.18 µm CMOS
Package 672-ball FineLine BGA (FC-FBGA) 672-ball FineLine BGA
Package Code BGA-652, 45 x 45 mm, 1.27 mm pitch —
Operating Temperature 0 °C to +85 °C (commercial) [DATA_NEEDED: operating temperature range]
Configuration SRAM-based, serial or parallel (EPC) —
Embedded Memory EAB blocks (dual-port RAM with byte enables) —
LVDS Support True-LVDS channels integrated —
MultiVolt I/O 1.8 V, 2.5 V, 3.3 V interfaces —
External Memory Interface DDR SDRAM, QDR SRAM —
JTAG Support IEEE 1149.1 boundary-scan —
RoHS Status [DATA_NEEDED: RoHS status] Lead-free / RoHS compliant (per Alibaba listing)
Typical Gates — 600,000
Maximum System Gates — 2,432,000
Maximum Logic Elements — 2,432
Embedded System Memory — 311,040 bits (380 Kbits ESB)
User I/O Pins — 488
Speed Grade — -3
PLLs — 4
Maximum Internal Frequency — 180 MHz (per APEX 20K family datasheet)
Configuration Modes — PS, PPS, PPA, JTAG, EPC2/EPC16
I/O Standards Supported — LVTTL, LVCMOS, SSTL-2/3, HSTL, LVDS, PCI
Mounting Type — Surface Mount

Datasheets & Resources

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