EP20K600CF672-3 vs EP20K600CF672-2 Comparison

Detailed side-by-side comparison of EP20K600CF672-3 by Intel and EP20K600CF672-2 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K600CF672-3 EP20K600CF672-2
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $99.50 $680.00
Family APEX 20KC β€”
Typical Gates 600,000 β€”
Maximum System Gates 2,432,000 β€”
Maximum Logic Elements 2,432 β€”
Embedded System Memory 311,040 bits (380 Kbits ESB) β€”
User I/O Pins 488 β€”
Package 672-ball FineLine BGA β€”
Speed Grade -3 -2
Process Technology 0.18 Β΅m CMOS 0.18 um CMOS
PLLs 4 β€”
Maximum Internal Frequency 180 MHz (per APEX 20K family datasheet) β€”
Configuration Modes PS, PPS, PPA, JTAG, EPC2/EPC16 β€”
I/O Standards Supported LVTTL, LVCMOS, SSTL-2/3, HSTL, LVDS, PCI β€”
Mounting Type Surface Mount Surface Mount
Operating Temperature [DATA_NEEDED: operating temperature range] 0 C to +60 C (TJ, per Alibaba supplier listing)
RoHS Status Lead-free / RoHS compliant (per Alibaba listing) [DATA_NEEDED: rohs_status]
Manufacturer β€” Intel / Altera
Series β€” APEX 20KC
Device Family β€” APEX 20KC PLD
Gate Count (typical) β€” 600,000 gates
Logic Elements β€” 30,720
Embedded RAM (approx.) β€” 311,232 bits
Package Type β€” 672-ball FineLine BGA (FCBGA)
Configuration Mode β€” Enhanced Configuration (EPC)
Number of PLLs β€” 4
I/O Standards β€” LVTTL, LVCMOS, and others per datasheet
Boundary Scan β€” IEEE 1149.1 (JTAG)
Lifecycle Status β€” Obsolete / last-time-buy

Datasheets & Resources

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