EP2AGX65CU17I5G vs EP2AGX65CU17I3G Comparison
Detailed side-by-side comparison of EP2AGX65CU17I5G by Intel and EP2AGX65CU17I3G by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2AGX65CU17I5G | EP2AGX65CU17I3G |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Unknown | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $218.00 |
| Device Type | Field Programmable Gate Array (FPGA) | β |
| Product Family | Arria II GX | β |
| Logic Elements | 60,214 | 60,214 |
| Programmable Logic Bits | 5,371,904 | β |
| User I/O Count | 156 | 156 |
| Package | 358-ball LFBGA, FCBGA | LFBGA-358 (FCBGA), 17x17 mm, 1.0 mm pitch |
| Number of Terminals | 358 | β |
| Terminal Form | Ball | β |
| Package Code | LFBGA | β |
| Package Shape | Square | β |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| Logic Cell Count | 60,214 | β |
| I/O Count | 156 | β |
| RoHS Status | Compliant | Compliant [DATA_NEEDED: confirm] |
| Lead Free Status | Not stated in verified data | β |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | β |
| Core Voltage | [DATA_NEEDED: core voltage] | β |
| I/O Voltage Support | [DATA_NEEDED: I/O voltage support] | β |
| Transceiver Count | [DATA_NEEDED: transceiver count] | β |
| Maximum Transceiver Data Rate | [DATA_NEEDED: maximum transceiver data rate] | β |
| Configuration Memory | [DATA_NEEDED: configuration memory] | β |
| Package Dimensions | [DATA_NEEDED: package dimensions] | β |
| Embedded Memory | [DATA_NEEDED: embedded memory] | β |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | β |
| Family | β | Arria II GX |
| Embedded Memory Bits | β | 5,371,904 |
| Embedded Memory Blocks | β | M9K (8 Kbit + 1 parity) [DATA_NEEDED: block count] |
| Embedded Multipliers (18x18) | β | 312 [DATA_NEEDED: confirm] |
| Transceivers | β | Up to 8 channels, 3.75 Gbps (GX) |
| PLLs | β | 8 [DATA_NEEDED: confirm] |
| PCIe Hard IP | β | Gen1 endpoint [DATA_NEEDED: confirm count] |
| Process Technology | β | 40 nm |
| Operating Temperature | β | -40C to +100C (industrial, "I") |
| Speed Grade | β | 3 |
| Supply Voltage (Core) | β | [DATA_NEEDED: VCC value] |