EP610DC-20 vs EP610ILC-10 Comparison
Detailed side-by-side comparison of EP610DC-20 by Intel and EP610ILC-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-20 | EP610ILC-10 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Product Type | CMOS UV-Erasable Programmable Logic Device (EPLD) | UV-Erasable / OTP PLD |
| Family | Classic EP610 | — |
| Logic Macrocells | 16 | — |
| Dedicated Inputs | 4 | 4 |
| I/O Pins | 16 (bidirectional) | 16 |
| Total Usable Pins | 20 | — |
| Product Terms (p-terms) | 160 | — |
| Propagation Delay (tPD) | 22 ns | — |
| Maximum Toggle Frequency (fMAX) | 55.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Operating Temperature | 0 °C to 70 °C (commercial) | [DATA_NEEDED: operating temperature range] |
| Package | 24-pin Ceramic DIP (CDIP-24) with UV window | PLCC-28 (plastic J-lead chip carrier) |
| Programming Method | UV erasure + parallel programmer | — |
| Process Technology | CMOS, UV-erasable floating gate | — |
| Mounting Type | Through-hole | Surface Mount (PLCC socket or solder) |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Family | — | Classic EPLD |
| Architecture | — | PAL-type with macrocells |
| Macrocells | — | 16 |
| Usable Gates | — | 300 |
| Product Terms | — | 160 |
| Supply Voltage | — | 5 V (single supply) |
| Pin-to-Pin Delay (tPD) | — | 10 ns (grade -10) |
| Counter Frequency (fCNT) | — | 100 MHz |
| Logic Family Compatibility | — | TTL (5 V CMOS/TTL-compatible I/O) |