EP610DC-25 vs EP610DI-35 Comparison
Detailed side-by-side comparison of EP610DC-25 by Rochester Electronics and EP610DI-35 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ ActiveIntel
EP610DI-35 - 16-Macrocell Classic EPLD, 35ns, 5V, 24-CDIP | Intel / Altera
EP610DI-35 ObsoleteSpecification Comparison
| Parameter | EP610DC-25 | EP610DI-35 |
|---|---|---|
| Brand | Rochester Electronics | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 16 | — |
| Equivalent Gates | 300 | — |
| Maximum Propagation Delay (tPD) | 25 ns | — |
| Pipelined Data Rate | Up to 100 MHz | — |
| Number of I/O Pins | 22 | — |
| Number of Dedicated Inputs | 4 | — |
| Total Pin Count | 24 | — |
| Package | 24-pin CDIP (Ceramic DIP, through-hole) | 24-pin CDIP (Ceramic DIP) |
| Mounting Type | Through Hole | Through-hole |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Operating Temperature | 0 C to +70 C | [DATA_NEEDED: industrial/commercial grade range] |
| Technology | CMOS EPROM (UV-erasable) | CMOS, UV-erasable |
| Programming Method | JEDEC fuse-map / UV-erase | — |
| Speed Grade Suffix | -25 (25 ns tPD) | — |
| Series | — | EP610 |
| Logic Cells / Macrocells | — | 16 macrocells |
| Usable Gates | — | 300 |
| Product Terms | — | 160 |
| I/O Pins | — | 16 bidirectional |
| Total Inputs | — | 20 (including 4 dedicated inputs) |
| Propagation Delay (tpd) | — | 35 ns |
| Maximum Toggle Frequency | — | 28.6 MHz |
| Internal Pipelined Data Rate | — | Up to 100 MHz |
| Supply Voltage | — | 5 V |
| RoHS Status | — | [DATA_NEEDED: not confirmed in supplied web data] |