EP610DC-35 vs EP610DI-25 Comparison
Detailed side-by-side comparison of EP610DC-35 by Altera and EP610DI-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-35 | EP610DI-25 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Device Type | CPLD - Classic EPLD | — |
| Family | Altera Classic EP610 | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 35 ns | 25 ns |
| Maximum Frequency (fMAX) | 28.6 MHz | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V nominal |
| Process Technology | CMOS | — |
| Program/erase Method | UV-erasable (windowed CERDIP) | — |
| Package | 24-pin CDIP (windowed CERDIP) 0.300 inch | — |
| Mounting Type | Through-Hole (DIP) | Through-Hole (DIP) |
| Operating Temperature | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] | Industrial (per "I" suffix) |
| Manufacturer | Originally Altera; today supplied via Rochester Electronics (authorized) | — |
| RoHS Status | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] | — |
| Part Family | — | Classic EPLD |
| Maximum Pipelined Clock Frequency | — | 100 MHz (max fCNT, per family datasheet) |
| I/O Pins | — | 16 (bidirectional) |
| Dedicated Inputs | — | 4 |
| Total User I/O | — | 20 |
| Technology | — | CMOS EPROM (UV-erasable) |
| Package Type | — | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 |
| Pin Count | — | 24 |
| Speed Grade Suffix | — | 25 = 25 ns |
| Compliance | — | RoHS status unknown (legacy 1990s part) |