EP610DC15 vs EP610DC-35 Comparison
Detailed side-by-side comparison of EP610DC15 by Intel and EP610DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC15 | EP610DC-35 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | NRND |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP610 Classic EPLD | Altera Classic EP610 |
| Macrocells | 16 | 16 |
| Architecture | PAL-type | — |
| Propagation Delay (tPD) | 15 ns | 35 ns |
| Maximum Clock Frequency (fMAX) | 71.4 MHz | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Total Inputs | 20 | — |
| I/O Lines | 16 | — |
| Product Terms | 160 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| Technology | CMOS | — |
| Operating Temperature | 0C to +70C | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Package | 24-pin CDIP (Ceramic DIP, windowed) | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Mounting Type | Through-Hole | Through-Hole (DIP) |
| Reprogrammability | Yes (UV erasable via windowed package) | — |
| RoHS Status | unknown | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Device Type | — | CPLD - Classic EPLD |
| Usable Gates | — | 300 |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Process Technology | — | CMOS |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |