EP610DI-30 vs EP610DC-25 Comparison
Detailed side-by-side comparison of EP610DI-30 by Rochester Electronics and EP610DC-25 by Rochester Electronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP610DI-30 - 16-Macrocell Classic EPLD, 30ns, CERDIP-24 | Rochester Electronics
EP610DI-30 ✓ ActiveRochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ ActiveSpecification Comparison
| Parameter | EP610DI-30 | EP610DC-25 |
|---|---|---|
| Brand | Rochester Electronics | Rochester Electronics |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic EP610 | Altera Classic EPLD |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 30 ns | — |
| Pipelined Data Rate | 100 MHz | Up to 100 MHz |
| Technology | CMOS | CMOS EPROM (UV-erasable) |
| Supply Voltage | 5 V (single supply) | — |
| Package | CERDIP-24 (windowed, UV-erasable) | 24-pin CDIP (Ceramic DIP, through-hole) |
| Mounting Type | Through-Hole | Through Hole |
| Programmable Elements | EPROM (UV-erasable, windowed) | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0 C to +70 C |
| I/O Pins | [DATA_NEEDED: I/O pin count] | — |
| Logic Capacity | [DATA_NEEDED: usable gates / logic capacity] | — |
| RoHS Status | unknown | — |
| Lead-Free | unknown | — |
| Original Manufacturer | Altera (now Intel) | — |
| Current Supplier | Rochester Electronics (authorized continuing source) | — |
| MSL Level | N/A (through-hole, non-surface-mount) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Equivalent Gates | — | 300 |
| Maximum Propagation Delay (tPD) | — | 25 ns |
| Number of I/O Pins | — | 22 |
| Number of Dedicated Inputs | — | 4 |
| Total Pin Count | — | 24 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Programming Method | — | JEDEC fuse-map / UV-erase |
| Speed Grade Suffix | — | -25 (25 ns tPD) |