EP610DI-35 vs EP610DC15 Comparison
Detailed side-by-side comparison of EP610DI-35 by Intel and EP610DC15 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP610DI-35 - 16-Macrocell Classic EPLD, 35ns, 5V, 24-CDIP | Intel / Altera
EP610DI-35 ObsoleteSpecification Comparison
| Parameter | EP610DI-35 | EP610DC15 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | Altera Classic EPLD | EP610 Classic EPLD |
| Series | EP610 | — |
| Logic Cells / Macrocells | 16 macrocells | — |
| Usable Gates | 300 | — |
| Product Terms | 160 | 160 |
| I/O Pins | 16 bidirectional | — |
| Total Inputs | 20 (including 4 dedicated inputs) | 20 |
| Propagation Delay (tpd) | 35 ns | — |
| Maximum Toggle Frequency | 28.6 MHz | — |
| Internal Pipelined Data Rate | Up to 100 MHz | — |
| Supply Voltage | 5 V | — |
| Technology | CMOS, UV-erasable | CMOS |
| Package | 24-pin CDIP (Ceramic DIP) | 24-pin CDIP (Ceramic DIP, windowed) |
| Mounting Type | Through-hole | Through-Hole |
| Operating Temperature | [DATA_NEEDED: industrial/commercial grade range] | 0C to +70C |
| RoHS Status | [DATA_NEEDED: not confirmed in supplied web data] | unknown |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 16 |
| Architecture | — | PAL-type |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Clock Frequency (fMAX) | — | 71.4 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| I/O Lines | — | 16 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Reprogrammability | — | Yes (UV erasable via windowed package) |