EP610DM-35 vs EP610DC-30 Comparison
Detailed side-by-side comparison of EP610DM-35 by Altera and EP610DC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DM-35 | EP610DC-30 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Manufacturer | Altera (Rochester Electronics authorized stock) | — |
| Part Family | Classic EPLD | — |
| Logic Family | PAL-type EPLD, CMOS, UV-erasable | — |
| Number of Macrocells | 16 | — |
| Number of Gates | 300 | — |
| Propagation Delay (tPD) | 35 ns | 30 ns |
| Pipelined Data Rate (fMAX) | 100 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| Package | 24-pin CDIP (CERDIP) with UV window | 24-pin CERDIP (windowed) |
| Temperature Grade (M) | Military -55°C to +125°C | — |
| I/O Pins | 24 dedicated I/O (input + bidirectional) | 16 (with output enable) |
| Programmability | UV-erasable, reprogrammable | UV-erasable, windowed EPROM |
| Operating Temperature Range | -55°C to +125°C | — |
| MSL Level | [DATA_NEEDED: MSL rating] | — |
| RoHS Status | Non-compliant (contains lead, hermetic CERDIP) | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP610 (Classic Device Family) |
| Macrocells | — | 16 |
| Logic Expanders | — | 4 (4 product terms per macrocell) |
| Usable Gates | — | 300 |
| Maximum Pipelined Clock Frequency | — | 100 MHz |
| Dedicated Inputs | — | 16 |
| Mounting Type | — | Through-Hole |
| Speed Grade | — | -30 (30 ns tPD) |
| Technology | — | CMOS EPROM |
| Security Bit | — | Yes (protects design after programming) |
| Output Modes | — | Registered and Combinatorial |
| Operating Temperature | — | Commercial (0C to +70C) |