EP610DM-35 vs EP610LI-30 Comparison
Detailed side-by-side comparison of EP610DM-35 by Altera and EP610LI-30 by Rochester Electronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DM-35 | EP610LI-30 |
|---|---|---|
| Brand | Altera | Rochester Electronics |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Manufacturer | Altera (Rochester Electronics authorized stock) | Rochester Electronics (originally Altera) |
| Part Family | Classic EPLD | — |
| Logic Family | PAL-type EPLD, CMOS, UV-erasable | — |
| Number of Macrocells | 16 | — |
| Number of Gates | 300 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Pipelined Data Rate (fMAX) | 100 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V (TTL-compatible I/O) |
| Package | 24-pin CDIP (CERDIP) with UV window | 24-pin Ceramic DIP (windowed, CDIP) |
| Temperature Grade (M) | Military -55°C to +125°C | — |
| I/O Pins | 24 dedicated I/O (input + bidirectional) | — |
| Programmability | UV-erasable, reprogrammable | — |
| Operating Temperature Range | -55°C to +125°C | — |
| MSL Level | [DATA_NEEDED: MSL rating] | — |
| RoHS Status | Non-compliant (contains lead, hermetic CERDIP) | unknown |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Classic EPLD (MAX architecture) |
| Macrocells | — | 16 |
| Pin-to-Pin Delay (tPD) | — | 30 ns |
| Maximum Internal Frequency (fMAX) | — | 100 MHz (pipelined) |
| AND Array | — | 24V16 |
| Process Technology | — | CMOS, UV-erasable EPROM cells |
| Operating Temperature | — | -55C to +125C (military/extended) |
| Output Polarity | — | User-configurable per macrocell |
| Flip-Flop per Cell | — | D / T / J-K configurable |
| Programming Method | — | UV erase + Classic-series PLD programmer |