EP610ILC-10 vs EP610ILC-25 Comparison
Detailed side-by-side comparison of EP610ILC-10 by Altera and EP610ILC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610ILC-10 | EP610ILC-25 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | Classic EPLD | — |
| Product Type | UV-Erasable / OTP PLD | — |
| Architecture | PAL-type with macrocells | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 |
| Product Terms | 160 | 160 |
| I/O Pins | 16 | — |
| Dedicated Inputs | 4 | 4 |
| Supply Voltage | 5 V (single supply) | — |
| Pin-to-Pin Delay (tPD) | 10 ns (grade -10) | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family Compatibility | TTL (5 V CMOS/TTL-compatible I/O) | — |
| Package | PLCC-28 (plastic J-lead chip carrier) | 28-pin PLCC (J-lead) |
| Mounting Type | Surface Mount (PLCC socket or solder) | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Family | — | Classic EPLD (EP610 series) |
| Device Type | — | EEPLD (Electrically Erasable PLD) |
| Maximum Operating Frequency (fMAX) | — | 40 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Nominal Supply Voltage | — | 5 V |
| Total Inputs | — | 20 |
| Bidirectional I/O Pins | — | 16 |
| Operating Temperature Range | — | 0 C to +70 C (commercial) |
| Process Technology | — | CMOS, electrically erasable |
| Programming Method | — | In-system, electrically erasable |