EP610ILC-25 vs EP610LC-25 Comparison
Detailed side-by-side comparison of EP610ILC-25 by Altera and EP610LC-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610ILC-25 | EP610LC-25 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Classic EPLD (EP610 series) | Classic EPLD |
| Device Type | EEPLD (Electrically Erasable PLD) | — |
| Usable Gates | 300 | — |
| Macrocells | 16 | 16 |
| Product Terms | 160 | — |
| Maximum Operating Frequency (fMAX) | 40 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Nominal Supply Voltage | 5 V | — |
| Total Inputs | 20 | — |
| Dedicated Inputs | 4 | — |
| Bidirectional I/O Pins | 16 | — |
| Operating Temperature Range | 0 C to +70 C (commercial) | — |
| Package | 28-pin PLCC (J-lead) | PLCC-28 |
| Mounting Type | Surface Mount | Surface Mount |
| Process Technology | CMOS, electrically erasable | — |
| Programming Method | In-system, electrically erasable | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED] |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 4 |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Toggle Frequency | — | 100 MHz |
| Pipelined Data Rate | — | Up to 100 MHz |
| Supply Voltage | — | 5 V ±5% |
| Technology | — | CMOS |
| Programmability | — | UV-erasable (windowed package) |
| Operating Temperature | — | 0C to +70C (commercial) |
| I/O Pins | — | [DATA_NEEDED: exact I/O count] |