EP610IPC-10 vs EP610IPC-25 Comparison
Detailed side-by-side comparison of EP610IPC-10 by Altera and EP610IPC-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610IPC-10 | EP610IPC-25 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | Altera Classic EPLD | Classic EPLD (EP610) |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Programmable Gates | 300 usable gates | — |
| Macrocells | 16 | — |
| Maximum Operating Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 15 ns (commerical -10 grade) | — |
| Product Terms | 160 total | 160 |
| Dedicated Inputs | 4 | — |
| I/O Pins | 16 | — |
| Total Input Pins | 20 | — |
| Supply Voltage | 5 V | — |
| Architecture | Turbo-only AND-OR-NOT, PAL-type | PAL-type, CMOS, Erasable |
| Technology | CMOS EPROM (UV-erasable / OTP) | CMOS, UV-erasable (windowless in IPC pkg) |
| Package | 24-pin PDIP (Plastic DIP) | 24-pin PDIP (Plastic DIP) |
| Operating Temperature | -40C to +85C (industrial) | 0 °C to +70 °C (Commercial) |
| Programming Method | Altera programming hardware (UV erase for I grade, OTP for C grade) | — |
| TTL Emulation | 100% TTL compatible | — |
| Propagation Delay (tpd) | — | 25 ns (max) |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Maximum Inputs | — | 20 |
| Maximum I/O Pins | — | 16 |
| Dedicated Outputs | — | 16 |
| TTL Compatibility | — | 100% TTL emulation |
| Mounting Type | — | Through-Hole |
| MSL Level | — | [DATA_NEEDED: MSL level] |
| RoHS Status | — | Non-compliant (contains Pb, PDIP package) |
| Logic Capacity | — | Equivalent to ~24 standard 24-pin PALs |