EP610IPC-10 vs EP610PC-20T Comparison
Detailed side-by-side comparison of EP610IPC-10 by Altera and EP610PC-20T by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610IPC-10 | EP610PC-20T |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.40 | $7.20 |
| Family | Altera Classic EPLD | Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | β |
| Programmable Gates | 300 usable gates | β |
| Macrocells | 16 | β |
| Maximum Operating Frequency | 100 MHz | β |
| Propagation Delay (tPD) | 15 ns (commerical -10 grade) | 20 ns |
| Product Terms | 160 total | β |
| Dedicated Inputs | 4 | β |
| I/O Pins | 16 | β |
| Total Input Pins | 20 | β |
| Supply Voltage | 5 V | β |
| Architecture | Turbo-only AND-OR-NOT, PAL-type | β |
| Technology | CMOS EPROM (UV-erasable / OTP) | β |
| Package | 24-pin PDIP (Plastic DIP) | 24-pin PDIP (Plastic DIP) |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (Commercial) |
| Programming Method | Altera programming hardware (UV erase for I grade, OTP for C grade) | β |
| TTL Emulation | 100% TTL compatible | β |
| Logic Elements / Macrocells | β | 16 macrocells |
| Usable Gates | β | 300 gates |
| Maximum Frequency (fMAX) | β | 62.5 MHz |
| Pipelined Data Rate | β | up to 100 MHz |
| Supply Voltage (VCC) | β | 5 V |
| Number of Dedicated Inputs | β | 16 |
| Number of I/O Pins | β | 16 |
| Programmable Output Enable | β | Yes (per macrocell) |
| Mounting Type | β | Through-Hole |
| Programming Technology | β | UV-erasable EPROM, CMOS |
| Development Tool | β | MAX+PLUS II |
| RoHS Status | β | unknown |