EP610LC-15 vs EP610IPC-25 Comparison
Detailed side-by-side comparison of EP610LC-15 by Altera and EP610IPC-25 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610LC-15 | EP610IPC-25 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD (EP610) | Classic EPLD (EP610) |
| Logic Elements / Macrocells | 16 macrocells | — |
| Equivalent Gates | 300 gates | — |
| Propagation Delay (tpd) | 15 ns | 25 ns (max) |
| Counter Frequency (fmax) | 83.3 MHz | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (Vcc) | 5 V (single supply) | — |
| Process Technology | CMOS | — |
| Package | 28-pin PLCC (J-lead, plastic OTP) | 24-pin PDIP (Plastic DIP) |
| Mounting Type | Surface Mount | Through-Hole |
| Number of Pins | 28 | — |
| Operating Temperature | 0C to +70C (commercial) [DATA_NEEDED: full temperature grade] | 0 °C to +70 °C (Commercial) |
| Programming | OTP (one-time programmable) | — |
| RoHS Status | unknown | Non-compliant (contains Pb, PDIP package) |
| MSL Level | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL level] |
| Architecture | — | PAL-type, CMOS, Erasable |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Maximum Inputs | — | 20 |
| Maximum I/O Pins | — | 16 |
| Dedicated Outputs | — | 16 |
| Product Terms | — | 160 |
| Technology | — | CMOS, UV-erasable (windowless in IPC pkg) |
| TTL Compatibility | — | 100% TTL emulation |
| Logic Capacity | — | Equivalent to ~24 standard 24-pin PALs |