EP610LI-30 vs EP610PC30 Comparison
Detailed side-by-side comparison of EP610LI-30 by Rochester Electronics and EP610PC30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610LI-30 | EP610PC30 |
|---|---|---|
| Brand | Rochester Electronics | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | NRND |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic EPLD (MAX architecture) | Classic EP610 |
| Macrocells | 16 | 16 |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Maximum Internal Frequency (fMAX) | 100 MHz (pipelined) | — |
| AND Array | 24V16 | — |
| Process Technology | CMOS, UV-erasable EPROM cells | — |
| Supply Voltage (VCC) | 5 V (TTL-compatible I/O) | 5 V |
| Package | 24-pin Ceramic DIP (windowed, CDIP) | PDIP-24 |
| Operating Temperature | -55C to +125C (military/extended) | [DATA_NEEDED: operating temperature range] |
| Output Polarity | User-configurable per macrocell | — |
| Flip-Flop per Cell | D / T / J-K configurable | — |
| Programming Method | UV erase + Classic-series PLD programmer | — |
| RoHS Status | unknown | Not applicable (legacy through-hole, contains Pb per historical datasheet) |
| Manufacturer | Rochester Electronics (originally Altera) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 300 |
| Propagation Delay (tPD) | — | 30 ns |
| Maximum Toggle Frequency | — | 33.3 MHz |
| Pipelined Data Rate | — | Up to 100 MHz |
| Technology | — | CMOS |
| Mounting Type | — | Through-Hole |
| Programming | — | EPROM/EEPROM-based, MAX+plus II toolchain |
| Logic Capacity | — | 16 macrocells / 300 gates equivalent |
| Configuration Memory | — | Non-volatile (UV-erasable or OTP variant) |
| Manufacturer (Original) | — | Altera Corporation (now Intel FPGA) |
| Current Distributor | — | Rochester Electronics, LLC |