EP610PC-20 vs EP610DC-15 Comparison
Detailed side-by-side comparison of EP610PC-20 by Altera and EP610DC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610PC-20 | EP610DC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Classic EPLD | — |
| Logic Elements | 16 macrocells | — |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 20 ns | 15 ns (speed grade -15) |
| Maximum Operating Frequency | 100 MHz (pipelined) | — |
| Supply Voltage (VCC) | 5 V ±10% | 4.75 V to 5.25 V |
| Number of Pins | 24 | — |
| Package | PDIP-24 | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Operating Temperature | 0C to +70C (commercial) | 0C to 70C (commercial) |
| Process Technology | CMOS EPROM | — |
| Programmable Flip-Flops | 16 | — |
| Input Pins | 24 | — |
| Output Pins | 16 | — |
| I/O Compatibility | TTL | — |
| Program/Erase Method | UV (windowed) or OTP | — |
| RoHS Status | Non-compliant (legacy PDIP) | [DATA_NEEDED: RoHS status] |
| Product Family | — | Classic EPLD (EP610) |
| Architecture | — | UV-erasable CMOS PAL-type |
| Macrocells | — | 16 |
| Logic Expanders | — | 4 |
| Dedicated Inputs | — | 20 |
| Bidirectional I/O Pins | — | 16 |
| Total Product Terms | — | 160 |
| Maximum Internal Clock Frequency | — | 71.4 MHz |
| Mounting Type | — | Through-Hole |
| Programming Method | — | JEDEC fuse map, UV erasure |
| Technology | — | CMOS |