EP610PC-20 vs EP610DC-15 Comparison
Detailed side-by-side comparison of EP610PC-20 by Altera and EP610DC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610PC-20 | EP610DC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $47.80 | $7.95 |
| Family | Classic EPLD | β |
| Logic Elements | 16 macrocells | β |
| Usable Gates | 300 | β |
| Propagation Delay (tPD) | 20 ns | 15 ns (speed grade -15) |
| Maximum Operating Frequency | 100 MHz (pipelined) | β |
| Supply Voltage (VCC) | 5 V Β±10% | 4.75 V to 5.25 V |
| Number of Pins | 24 | β |
| Package | PDIP-24 | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Operating Temperature | 0C to +70C (commercial) | 0C to 70C (commercial) |
| Process Technology | CMOS EPROM | β |
| Programmable Flip-Flops | 16 | β |
| Input Pins | 24 | β |
| Output Pins | 16 | β |
| I/O Compatibility | TTL | β |
| Program/Erase Method | UV (windowed) or OTP | β |
| RoHS Status | Non-compliant (legacy PDIP) | [DATA_NEEDED: RoHS status] |
| Product Family | β | Classic EPLD (EP610) |
| Architecture | β | UV-erasable CMOS PAL-type |
| Macrocells | β | 16 |
| Logic Expanders | β | 4 |
| Dedicated Inputs | β | 20 |
| Bidirectional I/O Pins | β | 16 |
| Total Product Terms | β | 160 |
| Maximum Internal Clock Frequency | β | 71.4 MHz |
| Mounting Type | β | Through-Hole |
| Programming Method | β | JEDEC fuse map, UV erasure |
| Technology | β | CMOS |