EP610PC-20 vs EP610PC-25 Comparison
Detailed side-by-side comparison of EP610PC-20 by Altera and EP610PC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610PC-20 | EP610PC-25 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Classic EPLD | — |
| Logic Elements | 16 macrocells | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 20 ns | — |
| Maximum Operating Frequency | 100 MHz (pipelined) | — |
| Supply Voltage (VCC) | 5 V ±10% | — |
| Number of Pins | 24 | — |
| Package | PDIP-24 | PDIP-24 (0.3 inch, through-hole) |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature grade] |
| Process Technology | CMOS EPROM | — |
| Programmable Flip-Flops | 16 | — |
| Input Pins | 24 | — |
| Output Pins | 16 | — |
| I/O Compatibility | TTL | — |
| Program/Erase Method | UV (windowed) or OTP | — |
| RoHS Status | Non-compliant (legacy PDIP) | [DATA_NEEDED: RoHS status] |
| Device Family | — | Classic EPLD (EP610 series) |
| Macro Cells | — | 16 |
| Propagation Delay (tpd) | — | 25 ns |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Technology | — | CMOS, EPROM (UV-erasable) |
| Device Type | — | OT PLD, PAL-type, CMOS |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 20 (bidirectional, JTAG-programmable OE per macrocell) |
| Programming Method | — | EPROM (UV-erasable), via Altera programming hardware |
| Mounting Type | — | Through-Hole (DIP) |