EP610PC-20T vs EP610PC-20 Comparison
Detailed side-by-side comparison of EP610PC-20T by Intel and EP610PC-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610PC-20T | EP610PC-20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | Classic EPLD | Classic EPLD |
| Logic Elements / Macrocells | 16 macrocells | — |
| Usable Gates | 300 gates | 300 |
| Propagation Delay (tPD) | 20 ns | 20 ns |
| Maximum Frequency (fMAX) | 62.5 MHz | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V ±10% |
| Number of Dedicated Inputs | 16 | — |
| Number of I/O Pins | 16 | — |
| Programmable Output Enable | Yes (per macrocell) | — |
| Package | 24-pin PDIP (Plastic DIP) | PDIP-24 |
| Mounting Type | Through-Hole | — |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Programming Technology | UV-erasable EPROM, CMOS | — |
| Development Tool | MAX+PLUS II | — |
| RoHS Status | unknown | Non-compliant (legacy PDIP) |
| Logic Elements | — | 16 macrocells |
| Maximum Operating Frequency | — | 100 MHz (pipelined) |
| Number of Pins | — | 24 |
| Process Technology | — | CMOS EPROM |
| Programmable Flip-Flops | — | 16 |
| Input Pins | — | 24 |
| Output Pins | — | 16 |
| I/O Compatibility | — | TTL |
| Program/Erase Method | — | UV (windowed) or OTP |