EP910IDC-15 vs EP910DC-40 Comparison
Detailed side-by-side comparison of EP910IDC-15 by Altera and EP910DC-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910IDC-15 | EP910DC-40 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $13.95 |
| Manufacturer | Altera (now Intel PSG) | β |
| Family | Classic EPLD | β |
| Equivalent Gates | 450 | β |
| Macrocells | 24 | 24 |
| Flip-Flops | 48 | β |
| Pin-to-Pin Delay (tPD) | 15 ns | β |
| Maximum Frequency (fCNT) | 66.6 MHz | β |
| Supply Voltage (VCC) | 5 V | β |
| Package | 40-pin CDIP (Ceramic DIP, through-hole) | DIP-40 (ceramic, through-hole) |
| Terminal Count | 40 | β |
| Terminal Form | Through-Hole | β |
| Temperature Grade | Commercial (0C to +70C) | β |
| Programmable Security Bit | Yes | β |
| On-board Test Circuitry | Yes | β |
| Logic Type | UV Erasable EPROM-based | β |
| I/O Pins | 24 | β |
| Dedicated Inputs | 10 | 12 |
| Programming Technology | EPROM (UV-erasable) | β |
| RoHS Status | non_compliant (ceramic DIP contains lead) | [DATA_NEEDED: rohs_status] |
| Device Family | β | Classic EPLD (EP910 series) |
| Architecture | β | PAL-type AND/OR, UV-erasable CMOS |
| Bidirectional I/O Pins | β | 24 |
| Total Inputs to Logic Array | β | 36 |
| Product Terms | β | 240 maximum |
| Maximum Propagation Delay (tPD) | β | 40 ns |
| Maximum Operating Frequency (fMAX) | β | 25 MHz |
| Global Clocks | β | 2 |
| Supply Voltage | β | 5 V (typical for Classic EPLD family) |
| Operating Temperature (Commercial) | β | 0 Β°C to 70 Β°C |
| Mounting Type | β | Through-Hole |
| Programming Method | β | UV-erase + EPROM programmer; on-board logic test circuitry |