EP910ILI-25 vs EP910DC-15 Comparison
Detailed side-by-side comparison of EP910ILI-25 by Altera and EP910DC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910ILI-25 | EP910DC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Series | EP910 (Classic EPLD) | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | — |
| Product Terms | 240 (maximum) | — |
| Propagation Delay (tPD) | 25 ns | — |
| Technology | CMOS, EPROM | CMOS EPROM, UV-erasable |
| Architecture | PAL-type with global interconnect bus | — |
| Package | PLCC-44 (windowed ceramic, J-lead) | 24-pin ceramic DIP (DC) |
| Operating Voltage | 5 V (4.75 V to 5.25 V) | — |
| Operating Temperature | -40C to +85C (Industrial) | 0C to +70C (commercial) |
| Programming Method | UV-erasable (windowed), MAX+PLUS II programmer | — |
| Logic Test Circuitry | On-board JTAG-compatible test | — |
| RoHS Status | Non-compliant (windowed ceramic package) | [DATA_NEEDED: not explicitly stated in verified data] |
| Family | — | Altera Classic EPLD |
| Device Density | — | 900 usable gates |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| Bidirectional I/O Pins | — | 12 |
| Flip-Flops | — | 10 |
| Product Terms per Macrocells | — | 24 |
| Maximum Propagation Delay (tPD) | — | 15 ns |
| Speed Grade | — | 15 |
| Supply Voltage (VCC) | — | 5 V (typical) |
| Mounting Type | — | Through-Hole |
| MSL Level | — | [DATA_NEEDED: MSL level] |