EP910IPC-12 vs EP910DC-30 Comparison
Detailed side-by-side comparison of EP910IPC-12 by Altera and EP910DC-30 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910IPC-12 | EP910DC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Classic EPLD | Classic EPLD (EP910 series) |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Maximum Operating Frequency (fMAX) | 76.9 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 12 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Dedicated Inputs | 10 | 36 |
| I/O Pins | 24 | — |
| Package | 40-pin PDIP | DIP-40 (through-hole, 600 mil) |
| Mounting Type | Through Hole | Through-Hole |
| Technology | CMOS EPLD (UV-erasable or OTP) | — |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Programming Toolchain | MAX+PLUS II | — |
| Logic Capacity | Equivalent to ~24 PAL16V8s | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | — |
| Architecture | — | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | — | 900 usable gates |
| Propagation Delay (tPD) | — | 30 ns (max) |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| Supply Voltage | — | 5 V |
| Process Technology | — | CMOS |
| Programming Method | — | UV-Erasable / OTP |