EP910IPC-25 vs EP910IPC-15 Comparison
Detailed side-by-side comparison of EP910IPC-25 by Intel and EP910IPC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910IPC-25 | EP910IPC-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Classic EPLD (EP910 series) | — |
| Manufacturer | Altera (now Intel) | — |
| Architecture | PAL-type EPLD, CMOS, UV/OTP | PAL-type, CMOS |
| Usable Gates | 450 | — |
| Macrocells | 24 | 24 |
| Product Terms | 240 | 240 |
| Propagation Delay (tPD) | 25 ns | 15 ns |
| Maximum Frequency (fMAX) | 40 MHz | — |
| Dedicated Inputs | 12 | 12 |
| Bidirectional I/O Lines | 24 | — |
| Total Inputs (max) | 36 | — |
| Total Outputs (max) | 24 | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V |
| Operating Temperature | 0C to +70C (commercial grade) | 0C to +70C (commercial, IPC suffix) |
| Package | 40-pin PDIP (PDIP-40) | PDIP-40 (Plastic DIP, 40-pin) |
| Mounting Type | Through-Hole | Through-Hole |
| Programming Method | EPROM cell (OTP / UV erasable) | JEDEC fuse map via Altera EPLD programmer |
| Development Tool | MAX+PLUS II | — |
| Device Family | — | Altera Classic EPLD (EP910 series) |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| I/O Pins | — | 24 |
| External Clocks | — | 2 |
| Process Technology | — | CMOS |
| Pin Count | — | 40 |
| RoHS Status | — | [DATA_NEEDED: rohs status not confirmed in verified data] |