EP910JC-35 vs EP910DM-40 Comparison
Detailed side-by-side comparison of EP910JC-35 by Altera and EP910DM-40 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910JC-35 | EP910DM-40 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $21.00 |
| Logic Family | Classic EPLD (CMOS EPROM) | β |
| Macrocells | 24 | 24 |
| Inputs | 36 | β |
| I/O Pins | 24 | β |
| Propagation Delay (max) | 38 ns (tPD) | β |
| Maximum Clock Frequency | 28.6 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | β |
| Operating Temperature | 0C to 70C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Package Type | 44-pin PLCC (Plastic J-Lead Chip Carrier) | β |
| Mounting Type | Surface Mount (PLCC socket recommended) | Through-Hole (DIP) |
| Terminal Form | J BEND | β |
| Package Code | QCCJ | β |
| Package Shape | SQUARE | β |
| Technology | CMOS EPROM, UV-erasable / OTP | β |
| RoHS Status | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance status] |
| Temperature Grading | COMMERCIAL | β |
| Equivalent Gates | Approx. 900 usable gates | β |
| Product Type | β | UV Erasable Programmable Logic Device (EPLD) |
| Family | β | Altera Classic EP910 |
| Architecture | β | PAL-type AND/OR with global programmable interconnect bus |
| Dedicated Inputs | β | 36 |
| Dedicated Outputs | β | 24 |
| Bidirectional I/O Lines | β | 24 |
| Product Terms | β | 240 |
| Propagation Delay (tPD) | β | 40 ns |
| External Clocks | β | 2 |
| Process Technology | β | CMOS |
| Package | β | 40-pin Ceramic DIP (Cerdip) with UV window |
| Supply Voltage | β | 5 V |
| Programming Interface | β | JEDEC-standard fuse-map / UV erasure |